公开(公告)号：US20070011474A1

公开(公告)日：2007-01-11

申请号：US11177369

申请日：2005-07-08

Applicant: Jenq-Kuen Lee ,  Yung-Chia Lin ,  Yi-Ping Yu ,  Chung-Wen Huang

Inventor： Jenq-Kuen Lee ,  Yung-Chia Lin ,  Yi-Ping Yu ,  Chung-Wen Huang

IPC: G06F1/00

CPC classification number: G06F1/3203

Abstract: A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.

Abstract translation: 处理器包括被配置为执行指令的多个执行单元，配置成从指令中筛选出功率切换指令的预解码器，以及配置成基于功率切换指令来控制执行单元的状态的功率控制器 。 功率控制器包括识别解码器，其被配置为从功率切换指令生成分别对应于执行单元的标识，以及功率管理器，被配置为切换与识别相对应的执行单元。 特别地，电源切换指令包括通电指令和断电指令。 处理器还包括多个预留表，每个预留表被配置为存储由执行单元中的一个执行的指令，并且关闭信号不被传送到功率管理器，直到与要执行的单元相对应的预约表被转动 关是空的。

公开(公告)号：US07398410B2

公开(公告)日：2008-07-08

申请号：US11177369

申请日：2005-07-08

Applicant: Jenq-Kuen Lee ,  Yung-Chia Lin ,  Yi-Ping Yu ,  Chung-Wen Huang

Inventor： Jenq-Kuen Lee ,  Yung-Chia Lin ,  Yi-Ping Yu ,  Chung-Wen Huang

IPC: G06F1/32

CPC classification number: G06F1/3203

Abstract: A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on the power-switching instruction. The power controller includes an identification decoder configured to generate identifications respectively corresponding to the execution units from the power-switching instruction, and a power manager configured to switch the execution unit corresponding to the identification. Particularly, the power-switching instruction includes a power-on instruction and a power-off instruction. The processor further includes a plurality of reservation tables each configured to store the instruction to be executed by one of the execution units, and a turn-off signal is not conveyed to the power manager until the reservation table corresponding to the execution unit to be turned off is empty.

Abstract translation: 处理器包括被配置为执行指令的多个执行单元，配置成从指令中筛选出功率切换指令的预解码器，以及配置成基于功率切换指令来控制执行单元的状态的功率控制器 。 功率控制器包括识别解码器，其被配置为从功率切换指令生成分别对应于执行单元的标识，以及功率管理器，被配置为切换与识别相对应的执行单元。 特别地，电源切换指令包括通电指令和断电指令。 处理器还包括多个预留表，每个预留表被配置为存储由执行单元中的一个执行的指令，并且关闭信号不被传送到功率管理器，直到与要执行的单元相对应的预约表被转动 关是空的。

公开(公告)号：US07650598B2

公开(公告)日：2010-01-19

申请号：US11463538

申请日：2006-08-09

Applicant: Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

Inventor： Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

IPC: G06F12/00

CPC classification number: G06F8/441

Abstract: A method of allocating registers for a PAC processor. The PAC processor has a first cluster and a second cluster. Each cluster includes a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment of the invention are performed to take full advantage of the properties of a PAC processor.

Abstract translation: 一种为PAC处理器分配寄存器的方法。 PAC处理器具有第一集群和第二集群。 每个集群包括第一功能单元，第二功能单元，连接到第一功能单元的第一本地寄存器文件，连接到第二寄存器堆的第二本地寄存器文件，以及具有乒乓结构的全局寄存器堆，所述乒乓结构由 第一个注册银行和第二个注册银行。 在构建组件/寄存器类型相关数据依赖关系图（CRTA-DDG）之后，执行本发明的功能单元分配，寄存器文件分配，乒乓寄存器组分配和集群分配，以充分利用 PAC处理器。

公开(公告)号：US20080052694A1

公开(公告)日：2008-02-28

申请号：US11463538

申请日：2006-08-09

Applicant: Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

Inventor： Jenq Kuen Lee ,  Yung Chia Lin ,  Yi Ping Yu

IPC: G06F9/45

CPC classification number: G06F8/441

Abstract: A method of allocating registers for a PAC processor. The PAC processor has a first cluster and a second cluster. Each cluster includes a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment of the invention are performed to take full advantage of the properties of a PAC processor.

Abstract translation: 一种为PAC处理器分配寄存器的方法。 PAC处理器具有第一集群和第二集群。 每个集群包括第一功能单元，第二功能单元，连接到第一功能单元的第一本地寄存器文件，连接到第二寄存器堆的第二本地寄存器文件以及具有乒乓结构的全局寄存器堆，所述乒乓结构由 第一个注册银行和第二个注册银行。 在构建组件/寄存器类型相关数据依赖关系图（CRTA-DDG）之后，执行本发明的功能单元分配，寄存器文件分配，乒乓寄存器组分配和集群分配，以充分利用 PAC处理器。