公开(公告)号：US08258831B1

公开(公告)日：2012-09-04

申请号：US12851280

申请日：2010-08-05

申请人： Yiftach Banai ,  Reuven Ecker

发明人： Yiftach Banai ,  Reuven Ecker

IPC分类号： H03L7/06

CPC分类号： H03L7/095

摘要： A clock generator is disclosed that includes a lock detector. The lock detector is configured to generate a lock signal based on control signals of a phase lock loop circuit that generates an output clock of a desired frequency that is phase locked to a reference clock. The lock detector generates a mismatch signal based on a comparison between the phases of the reference clock and the output clock to generate a compare result. The lock detector delays the compare result by a time period Td and AND the delayed compare result with the compare result to generate the mismatch signal. The lock detector includes a lock-counter that counts a number of reference clock cycles when the mismatch signal remains at 0. The lock signal indicates that a lock-state is achieved when the number of counted reference clock cycles equals a set-value.

摘要翻译： 公开了一种包括锁定检测器的时钟发生器。 锁定检测器被配置为基于产生相位锁定到参考时钟的期望频率的输出时钟的锁相环电路的控制信号产生锁定信号。 锁定检测器基于参考时钟的相位与输出时钟之间的比较产生失配信号，以产生比较结果。 锁定检测器将比较结果延迟时间段Td，并将延迟的比较结果与比较结果进行AND延迟，以产生失配信号。 锁定检测器包括锁定计数器，当不匹配信号保持为0时，对计数多个参考时钟周期的锁定计数器。锁定信号指示当计数的参考时钟周期数等于设定值时，锁定状态得以实现。

公开(公告)号：US07652516B2

公开(公告)日：2010-01-26

申请号：US11876526

申请日：2007-10-22

申请人： Ido Bourstein ,  Yiftach Banai ,  Gil Stoler

发明人： Ido Bourstein ,  Yiftach Banai ,  Gil Stoler

IPC分类号： H03K3/00

CPC分类号： H03K5/135 ,  G06F1/08 ,  G11C7/22 ,  G11C7/222

摘要： A apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

摘要翻译： 公开了一种用于产生一个或多个时钟信号的装置和方法。 基于模式信号和参考时钟信号产生时钟信号。 当参考时钟信号变为高电平时，输出第一模式信号的状态，并且当参考时钟信号变为低电平时，输出第二模式信号的状态。 根据参考时钟信号选择的第一和第二模式信号的连续状态提供所生成的时钟信号。

公开(公告)号：US20080094117A1

公开(公告)日：2008-04-24

申请号：US11876526

申请日：2007-10-22

申请人： Gil Stoler ,  Ido Bourstein ,  Yiftach Banai

发明人： Gil Stoler ,  Ido Bourstein ,  Yiftach Banai

IPC分类号： H03L7/06

CPC分类号： H03K5/135 ,  G06F1/08 ,  G11C7/22 ,  G11C7/222

摘要： A apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

摘要翻译： 公开了一种用于产生一个或多个时钟信号的装置和方法。 基于模式信号和参考时钟信号产生时钟信号。 当参考时钟信号变为高电平时，输出第一模式信号的状态，并且当参考时钟信号变为低电平时，输出第二模式信号的状态。 根据参考时钟信号选择的第一和第二模式信号的连续状态提供所生成的时钟信号。

公开(公告)号：US07932768B2

公开(公告)日：2011-04-26

申请号：US12650125

申请日：2009-12-30

申请人： Ido Bourstein ,  Yiftach Banai ,  Gil Stoler

发明人： Ido Bourstein ,  Yiftach Banai ,  Gil Stoler

IPC分类号： H03K3/00

CPC分类号： H03K5/135 ,  G06F1/08 ,  G11C7/22 ,  G11C7/222

摘要： An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

摘要翻译： 公开了用于产生一个或多个时钟信号的装置和方法。 基于模式信号和参考时钟信号产生时钟信号。 当参考时钟信号变为高电平时，输出第一模式信号的状态，并且当参考时钟信号变为低电平时，输出第二模式信号的状态。 根据参考时钟信号选择的第一和第二模式信号的连续状态提供所生成的时钟信号。

公开(公告)号：US20100102869A1

公开(公告)日：2010-04-29

申请号：US12650125

申请日：2009-12-30

申请人： Gil Stoler ,  Ido Bourstein ,  Yiftach Banai

发明人： Gil Stoler ,  Ido Bourstein ,  Yiftach Banai

IPC分类号： G06F1/04

CPC分类号： H03K5/135 ,  G06F1/08 ,  G11C7/22 ,  G11C7/222

摘要： An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

摘要翻译： 公开了用于产生一个或多个时钟信号的装置和方法。 基于模式信号和参考时钟信号产生时钟信号。 当参考时钟信号变为高电平时，输出第一模式信号的状态，并且当参考时钟信号变为低电平时，输出第二模式信号的状态。 根据参考时钟信号选择的第一和第二模式信号的连续状态提供所生成的时钟信号。