公开(公告)号：US5255130A

公开(公告)日：1993-10-19

申请号：US678086

申请日：1991-03-29

申请人： William A. Buchan ,  Gregory A. Unruh ,  Yinyi Lin

发明人： William A. Buchan ,  Gregory A. Unruh ,  Yinyi Lin

IPC分类号： G06F3/06 ,  G11B5/09 ,  G11B20/10 ,  G11B27/36 ,  G11B20/14 ,  H03K3/017 ,  H03K5/06

CPC分类号： G11B20/10194 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10481 ,  G11B27/36 ,  G11B5/09

摘要： A write equalization circuit that includes a data encoder for producing a binary data signal wherein a 1 is represented by a transition at the start of a bit interval and a 0 is represented by no transition at the start of a bit interval, an equalization timing generator for generating a start signal indicative of the initial edges of equalization pulses for predetermined 0's in the binary data signal, and a multiple stage delay delay circuit having logic gates implemented in an integrated circuit and responsive to the start signal and a control word for providing equalization pulses of a substantially constant width, wherein the number of stages employed for delay is determined by the control word. Logic circuitry implemented in the same integrated circuit as the multiple stage delay circuit detects changes in the propagation delay characteristics of the logic gates of the multiple stage delay circuit, and a processor responsive to the logic circuitry adjusts the control word so as to maintain the width of the equalization pulses substantially constant. Also disclosed is a method for adjusting write equalization pulses in a tape drive to achieve a desired suppression in the read signal.

公开(公告)号：US5267096A

公开(公告)日：1993-11-30

申请号：US838187

申请日：1992-02-18

申请人： William A. Buchan ,  Gregory A. Unruh ,  Yinyi Lin

发明人： William A. Buchan ,  Gregory A. Unruh ,  Yinyi Lin

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B27/36

CPC分类号： G11B20/10194 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10481 ,  G11B27/36 ,  G11B5/09

摘要： A write equalization circuit that includes a data encoder for producing a binary data signal wherein a 1 is represented by a transition at the start of a bit interval and a 0 is represented by no transition at the start of a bit interval, and a nominal pulse generating circuit for producing nominal equalization pulses respectively synchronized with predetermined 0's in the binary signal. Adjusting circuitry responsive to the binary data signal and the nominal equalization pulses produces a write data signal that includes equalization pulses having a width and location in bit intervals that remain substantially constant with changes in component delays due to changing temperature and voltage, wherein the constant width and location of the equalization pulses are selected to achieve a predetermined suppression characteristic.

摘要翻译： 一种写均衡电路，包括用于产生二进制数据信号的数据编码器，其中a由位间隔开始时的转换表示，0表示在位间隔开始时无转换，标称脉冲 产生分别与二进制信号中的预定0相同步的标称均衡脉冲的电路。 响应于二进制数据信号和标称均衡脉冲的调节电路产生写入数据信号，该写入数据信号包括均匀脉冲，该均衡脉冲具有以比特间隔的宽度和位置，其随着温度和电压的变化而随分量延迟的变化而保持基本恒定，其中恒定宽度 并且选择均衡脉冲的位置以实现预定的抑制特性。