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公开(公告)号：US5255130A
公开(公告)日：1993-10-19
申请号：US678086
申请日：1991-03-29
申请人： William A. Buchan , Gregory A. Unruh , Yinyi Lin
发明人： William A. Buchan , Gregory A. Unruh , Yinyi Lin
CPC分类号： G11B20/10194 , G11B20/10009 , G11B20/10046 , G11B20/10481 , G11B27/36 , G11B5/09
摘要： A write equalization circuit that includes a data encoder for producing a binary data signal wherein a 1 is represented by a transition at the start of a bit interval and a 0 is represented by no transition at the start of a bit interval, an equalization timing generator for generating a start signal indicative of the initial edges of equalization pulses for predetermined 0's in the binary data signal, and a multiple stage delay delay circuit having logic gates implemented in an integrated circuit and responsive to the start signal and a control word for providing equalization pulses of a substantially constant width, wherein the number of stages employed for delay is determined by the control word. Logic circuitry implemented in the same integrated circuit as the multiple stage delay circuit detects changes in the propagation delay characteristics of the logic gates of the multiple stage delay circuit, and a processor responsive to the logic circuitry adjusts the control word so as to maintain the width of the equalization pulses substantially constant. Also disclosed is a method for adjusting write equalization pulses in a tape drive to achieve a desired suppression in the read signal.
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公开(公告)号：US5267096A
公开(公告)日：1993-11-30
申请号：US838187
申请日：1992-02-18
申请人： William A. Buchan , Gregory A. Unruh , Yinyi Lin
发明人： William A. Buchan , Gregory A. Unruh , Yinyi Lin
CPC分类号： G11B20/10194 , G11B20/10009 , G11B20/10046 , G11B20/10481 , G11B27/36 , G11B5/09
摘要： A write equalization circuit that includes a data encoder for producing a binary data signal wherein a 1 is represented by a transition at the start of a bit interval and a 0 is represented by no transition at the start of a bit interval, and a nominal pulse generating circuit for producing nominal equalization pulses respectively synchronized with predetermined 0's in the binary signal. Adjusting circuitry responsive to the binary data signal and the nominal equalization pulses produces a write data signal that includes equalization pulses having a width and location in bit intervals that remain substantially constant with changes in component delays due to changing temperature and voltage, wherein the constant width and location of the equalization pulses are selected to achieve a predetermined suppression characteristic.
摘要翻译： 一种写均衡电路，包括用于产生二进制数据信号的数据编码器，其中a由位间隔开始时的转换表示，0表示在位间隔开始时无转换，标称脉冲 产生分别与二进制信号中的预定0相同步的标称均衡脉冲的电路。 响应于二进制数据信号和标称均衡脉冲的调节电路产生写入数据信号，该写入数据信号包括均匀脉冲，该均衡脉冲具有以比特间隔的宽度和位置，其随着温度和电压的变化而随分量延迟的变化而保持基本恒定，其中恒定宽度 并且选择均衡脉冲的位置以实现预定的抑制特性。
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公开(公告)号：US07624328B2
公开(公告)日：2009-11-24
申请号：US11198011
申请日：2005-08-04
申请人： Gregory A. Unruh
发明人： Gregory A. Unruh
IPC分类号： H03M13/00
CPC分类号： G06F11/1008
摘要： Data error detection comprises storing in a first buffer data to be written to a medium and a first digital signature of the data. If the first digital signature matches a second digital signature of data read from the first buffer, a compressed form of data read from the first buffer is stored in a FIFO. If the first digital signature matches a third digital signature of an uncompressed form of the compressed data, the uncompressed form of the compressed data, a C2 ECC of a first C1 ECC of the uncompressed form of the compressed data, and one or more C1 ECCs comprising the first C1 ECC and a second C1 ECC of the C2 ECC are stored in a second buffer. Success is indicated if the one or more C1 ECCs match corresponding C1 ECCs calculated from data and C1 ECCs read from the second buffer, and if a C1 ECC of the data read from the second buffer and written to a medium matches a C1 ECC of corresponding data read back from the medium.
摘要翻译： 数据错误检测包括将要写入介质的第一缓冲器数据和数据的第一数字签名存储。 如果第一数字签名匹配从第一缓冲器读取的数据的第二数字签名，则从第一缓冲器读取的压缩形式的数据被存储在FIFO中。 如果第一数字签名匹配压缩数据的未压缩形式的第三数字签名，则压缩数据的未压缩形式，压缩数据的未压缩形式的第一C1 ECC的C2 ECC和一个或多个C1 ECC 包括第一C1 ECC和C2 ECC的第二C1 ECC存储在第二缓冲器中。 如果一个或多个C1 ECC与从第二缓冲器读取的数据和C1 ECC计算的相应C1 ECC匹配，并且如果从第二缓冲器读取并写入到介质的C1 ECC的C1 ECC匹配相应的C1 ECC 数据从介质读回。
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4.发明授权
公开(公告)号：US5969894A
公开(公告)日：1999-10-19
申请号：US219309
申请日：1998-12-23
CPC分类号： G11B20/1419 , G11B5/09 , H03L7/08 , H03L7/183
摘要： A data detection circuit for a read channel that recovers data encoded as the presence or absence of flux transitions on a magnetic recording medium, compares a current data sample of a read signal with a previous data sample and a threshold to determine whether the previous data sample represents a flux transition. The use of two data samples in the determination of flux transitions provides a more accurate detection of the data than comparing a single data sample to a threshold value. The data detection circuit generates an output data signal having data values based on the determined flux transitions of the data samples.
摘要翻译： 用于读取通道的数据检测电路，其恢复被编码为磁记录介质上存在或不存在通量转换的数据，将读取信号的当前数据样本与先前数据样本和阈值进行比较，以确定先前数据样本 表示通量过渡。 在确定通量转换中使用两个数据样本提供比将单个数据样本与阈值进行比较更准确的数据检测。 数据检测电路产生具有基于所确定的数据采样的通量转换的数据值的输出数据信号。
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公开(公告)号：US20080172594A1
公开(公告)日：2008-07-17
申请号：US11198011
申请日：2005-08-04
申请人： Gregory A. Unruh
发明人： Gregory A. Unruh
CPC分类号： G06F11/1008
摘要： Data error detection comprises storing in a first buffer data to be written to a medium and a first digital signature of the data. If the first digital signature matches a second digital signature of data read from the first buffer, a compressed form of data read from the first buffer is stored in a FIFO. If the first digital signature matches a third digital signature of an uncompressed form of the compressed data, the uncompressed form of the compressed data, a C2 ECC of a first C1 ECC of the uncompressed form of the compressed data, and one or more C1 ECCs comprising the first C1 ECC and a second C1 ECC of the C2 ECC are stored in a second buffer. Success is indicated if the one or more C1 ECCs match corresponding C1 ECCs calculated from data and C1 ECCs read from the second buffer, and if a C1 ECC of the data read from the second buffer and written to a medium matches a C1 ECC of corresponding data read back from the medium.
摘要翻译： 数据错误检测包括将要写入介质的第一缓冲器数据和数据的第一数字签名存储。 如果第一数字签名匹配从第一缓冲器读取的数据的第二数字签名，则从第一缓冲器读取的压缩形式的数据被存储在FIFO中。 如果第一数字签名匹配压缩数据的未压缩形式的第三数字签名，则压缩数据的未压缩形式，压缩数据的未压缩形式的第一C1 ECC的C2 ECC和一个或多个C1 ECC 包括第一C1 ECC和C2 ECC的第二C1 ECC存储在第二缓冲器中。 如果一个或多个C1 ECC与从第二缓冲器读取的数据和C1 ECC计算的相应C1 ECC相匹配，并且如果从第二缓冲区读取并写入介质的C1 ECC的C1 ECC匹配相应的C1 ECC 数据从介质读回。
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6.发明授权Method and an arrangement for detecting state transitions in a read signal during a bit cell timing window 失效用于在比特单元定时窗口期间检测读取信号中的状态转换的方法和装置
公开(公告)号：US5892631A
公开(公告)日：1999-04-06
申请号：US525232
申请日：1995-09-08
CPC分类号： G11B20/1419 , G11B5/09 , H03L7/08 , H03L7/183
摘要： A data detection circuit for a read channel that recovers data encoded as the presence or absence of flux transitions on a magnetic recording medium, compares a current data sample of a read signal with a previous data sample and a threshold to determine whether the previous data sample represents a flux transition. The use of two data samples in the determination of flux transitions provides a more accurate detection of the data than comparing a single data sample to a threshold value. The data detection circuit generates an output data signal having data values based on the determined flux transitions of the data samples.
摘要翻译： 用于读取通道的数据检测电路，其恢复被编码为磁记录介质上存在或不存在通量转换的数据，将读取信号的当前数据样本与先前数据样本和阈值进行比较，以确定先前数据样本 表示通量过渡。 在确定通量转换中使用两个数据样本提供比将单个数据样本与阈值进行比较更准确的数据检测。 数据检测电路产生具有基于所确定的数据采样的通量转换的数据值的输出数据信号。
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