公开(公告)号：US07428682B2

公开(公告)日：2008-09-23

申请号：US11335464

申请日：2006-01-20

申请人： Yoichiro Aihara ,  Masahiko Nishiyama ,  Daisuke Sasaki

发明人： Yoichiro Aihara ,  Masahiko Nishiyama ,  Daisuke Sasaki

IPC分类号： G01R31/28

CPC分类号： G11C29/36 ,  G01R31/31723 ,  G01R31/31813 ,  G11C15/00 ,  G11C2029/3602

摘要： In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and in number of LSI pins, and further, to facilitate mounting on chips. The data generators for CAM testing, inserted between the APG for RAMs and CAM macros, create data to write to the CAM macros by obtaining the address signals directly or by decoding the same signals. The APG is common to all the memory macros, and testing proper to each CAM can be carried out by changing over the operation of the inserted data generators by means of the control signal. The data generators are arranged in the proximity of the CAM macros, the circuits to be tested.

摘要翻译： 关于用于测试CAM宏的内置自检电路（BIST电路），本发明旨在提供一种能够减少用于信号分配，缓冲器，FF等的布线沟道区域所需的材料量的装置， 等等，并且以LSI引脚的数量，并且进一步，以便于安装在芯片上。 用于CAM测试的数据生成器插入到RAM的APG和CAM宏之间，通过直接获取地址信号或通过解码相同的信号来创建数据写入CAM宏。 APG对于所有存储器宏是通用的，并且可以通过利用控制信号改变插入的数据发生器的操作来执行每个CAM的适当测试。 数据发生器安排在CAM宏附近，要测试的电路。

公开(公告)号：US20060195743A1

公开(公告)日：2006-08-31

申请号：US11335464

申请日：2006-01-20

申请人： Yoichiro Aihara ,  Masahiko Nishiyama ,  Daisuke Sasaki

发明人： Yoichiro Aihara ,  Masahiko Nishiyama ,  Daisuke Sasaki

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/36 ,  G01R31/31723 ,  G01R31/31813 ,  G11C15/00 ,  G11C2029/3602

摘要： In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and in number of LSI pins, and further, to facilitate mounting on chips. The data generators for CAM testing, inserted between the APG for RAMs and CAM macros, create data to write to the CAM macros by obtaining the address signals directly or by decoding the same signals. The APG is common to all the memory macros, and testing proper to each CAM can be carried out by changing over the operation of the inserted data generators by means of the control signal. The data generators are arranged in the proximity of the CAM macros, the circuits to be tested.

摘要翻译： 关于用于测试CAM宏的内置自检电路（BIST电路），本发明旨在提供一种能够减少用于信号分配，缓冲器，FF等的布线沟道区域所需的材料量的装置， 等等，并且以LSI引脚的数量，并且进一步，以便于安装在芯片上。 用于CAM测试的数据生成器插入到RAM的APG和CAM宏之间，通过直接获取地址信号或通过解码相同的信号来创建数据写入CAM宏。 APG对于所有存储器宏是通用的，并且可以通过利用控制信号改变插入的数据发生器的操作来执行每个CAM的适当测试。 数据发生器安排在CAM宏附近，要测试的电路。

公开(公告)号：US20050146947A1

公开(公告)日：2005-07-07

申请号：US11011427

申请日：2004-12-15

申请人： Keiichi Higeta ,  Satoshi Iwahashi ,  Yoichiro Aihara ,  Shigeru Nakahara

发明人： Keiichi Higeta ,  Satoshi Iwahashi ,  Yoichiro Aihara ,  Shigeru Nakahara

IPC分类号： G11C15/04 ,  G11C16/04 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L27/11 ,  G11C15/04 ,  G11C15/043 ,  H01L27/1104

摘要： Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

摘要翻译： 数据线（D 0，D 1）由第一存储部分（MA）和第二存储部分（MB）共享，此外，第一晶体管（MC 0）耦合到第一比较数据部分（CD 0）和 耦合到第一存储部分的存储节点的第二晶体管（MCA）串联连接以形成第一比较电路（11）和耦合到第二比较数据线（CD 1）的第三晶体管（MC 1）和 耦合到第二存储部分的存储节点的第四晶体管（MCB）串联连接以形成第二比较电路（12）。 因此，可以提高扩散层和布线层的布局的对称性，并且实现存储单元相对于穿过其中心的中心线线对称的布局的容易性。 因此，可以容易地优化制造工艺条件，并且可以降低制造工艺的变化，从而可以实现存储单元的微细加工。

公开(公告)号：US07009862B2

公开(公告)日：2006-03-07

申请号：US11011427

申请日：2004-12-15

申请人： Keiichi Higeta ,  Satoshi Iwahashi ,  Yoichiro Aihara ,  Shigeru Nakahara

发明人： Keiichi Higeta ,  Satoshi Iwahashi ,  Yoichiro Aihara ,  Shigeru Nakahara

IPC分类号： G11C7/00

CPC分类号： H01L27/11 ,  G11C15/04 ,  G11C15/043 ,  H01L27/1104

摘要： Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

摘要翻译： 数据线（D 0，D 1）由第一存储部分（MA）和第二存储部分（MB）共享，此外，第一晶体管（MC 0）耦合到第一比较数据部分（CD 0）和 耦合到第一存储部分的存储节点的第二晶体管（MCA）串联连接以形成第一比较电路（11）和耦合到第二比较数据线（CD 1）的第三晶体管（MC 1）和 耦合到第二存储部分的存储节点的第四晶体管（MCB）串联连接以形成第二比较电路（12）。 因此，可以提高扩散层和布线层的布局的对称性，并且实现存储单元相对于穿过其中心的中心线线对称的布局的容易性。 因此，可以容易地优化制造工艺条件，并且可以降低制造工艺的变化，从而可以实现存储单元的微细加工。