利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.012 秒)

    Clock generating apparatus for skew control between two-phase non-overlapping clocks
    2.
    发明授权
    Clock generating apparatus for skew control between two-phase non-overlapping clocks 失效
    用于两相非重叠时钟之间的偏移控制的时钟发生装置

    公开(公告)号：US6073246A

    公开(公告)日：2000-06-06

    申请号：US106856

    申请日：1998-06-30

    申请人： Yoon Seok Song ,  Sung Sik Lee

    发明人： Yoon Seok Song ,  Sung Sik Lee

    IPC分类号： G06F1/12 ,  G06F1/10

    CPC分类号： G06F1/10

    摘要： This invention provides a clock generating apparatus that can control a skew between two-phase non-overlapping clocks in order to maintain constant non-overlapping period through an accurate analysis for the clock skew by a simple programming of delay. The invention has a delay block that receives first and second clock signals as inputs, and outputs them with delay. The invention also can control every skew in the chip and non-overlapping period of the first and the second clock signal by constituting the delay block being programmable.

    摘要翻译： 本发明提供了一种时钟发生装置，其可以控制两相非重叠时钟之间的偏斜，以便通过简单的延迟编程通过对时钟偏移的精确分析来保持恒定的非重叠周期。 本发明具有接收第一和第二时钟信号作为输入并延迟输出的延迟块。 本发明还可以通过构成可编程的延迟块来控制第一和第二时钟信号的芯片的每个偏移和非重叠周期。

    Apparatus for controlling power sequence of an LCD module
    3.
    发明授权
    Apparatus for controlling power sequence of an LCD module 失效
    用于控制LCD模块的功率顺序的装置

    公开(公告)号：US5777611A

    公开(公告)日：1998-07-07

    申请号：US649509

    申请日：1996-05-17

    申请人： Yoon Seok Song

    发明人： Yoon Seok Song

    IPC分类号： G09G3/36 ,  G09G5/00

    CPC分类号： G09G3/36 ,  G09G2330/02

    摘要： The present invention relates to an apparatus for sequentially controlling power to operate an LCD module through the internal circuit of an LCD controller, and comprises a timing and comparing means for receiving a timer value and a clock signal from an external circuit and outputting a match signal to control a time interval to sequentially generate said enable signals and to sequentially disable said enable signals; a display control means for controlling said display responsive to a display control signal, a write control signal and a reset signal from said external circuit; a power sequence FSM (finite state machine) for receiving the output of said display control means, said match signal from said timing and comparing means, said clock signal from an external circuit and a FSM reset signal, and outputting a clear signal to said timing and comparing means or outputting a first and second power enable signals and a control enable signal to said display; and a FSM reset signal generating means for receiving said reset signal from said external circuit and said first and second power enable signals and said control enable signal from said power sequence FSM, and outputting said FSM reset signal to said power sequence FSM in order to mask said first and second power enable signals and said control enable signal.

    摘要翻译： 本发明涉及一种用于顺序地控制通过LCD控制器的内部电路操作LCD模块的电源的装置，并且包括一个定时和比较装置，用于从外部电路接收定时器值和时钟信号并输出​​匹配信号 以控制时间间隔以顺序地产生所述使能信号并且顺序地禁用所述使能信号; 显示控制装置，用于响应于来自所述外部电路的显示控制信号，写控制信号和复位信号来控制所述显示; 用于接收所述显示控制装置的输出的功率序列FSM（有限状态机），来自所述定时的所述匹配信号和比较装置，来自外部电路的所述时钟信号和FSM复位信号，并将清除信号输出到所述定时 以及比较装置或将第一和第二功率使能信号和控制使能信号输出到所述显示器; 以及FSM复位信号发生装置，用于从所述外部电路接收所述复位信号，以及从所述功率序列FSM接收所述第一和第二功率使能信号和所述控制使能信号，并将所述FSM复位信号输出到所述功率序列FSM以掩蔽 所述第一和第二功率使能信号和所述控制使能信号。

    Apparatus and method for converting floating point number into integer in floating point unit
    5.
    发明授权
    Apparatus and method for converting floating point number into integer in floating point unit 失效
    将浮点数转换成整数的装置和方法

    公开(公告)号：US6151612A

    公开(公告)日：2000-11-21

    申请号：US74601

    申请日：1998-05-08

    申请人： Yoon Seok Song

    发明人： Yoon Seok Song

    IPC分类号： H03M7/24 ,  G06F5/00

    CPC分类号： H03M7/24

    摘要： The present invention relates to an apparatus and a method for converting the binary floating point number into a integer represented as binary numbers of fixed length, the method for converting the binary floating point number into a integer comprising: calculating an exponent difference between the floating point number as a first operand and a constant which has a fraction of `0` value and an exponent of `data sizes of the integer-1` value as a second operand, shifting the fraction of the operand having the smaller exponent as many as the exponent difference, and outputting a bigger exponent; adding the fraction of the operand having the bigger exponent and a selected fraction, wherein the a selected fraction is in case of a negative value, the shifted fraction which is complemented to one, in case of a positive value, the shifted fraction itself in response to a sign of the first operand; and outputting the bigger exponent as a final result of the exponent, outputting and rounding the added fraction in response to a control signal as the final result of the fraction.

    摘要翻译： 本发明涉及一种用于将二进制浮点数转换为固定长度二进制数的整数的装置和方法，用于将二进制浮点数转换成整数的方法包括：计算浮点数之间的指数差 数字作为第一操作数，并且具有“0”的一小部分和“数据大小为整数-1”值的指数作为第二操作数的常数，将具有指数小的操作数的分数移位到与 指数差，并输出较大的指数; 添加具有较大指数的操作数的分数和选择的分数，其中所选择的分数在负值的情况下，在正值的情况下补充为1的偏移分数是响应中的偏移分数本身 到第一个操作数的标志; 并输出较大的指数作为指数的最终结果，响应于作为分数的最终结果的控制信号输出和舍入加法分数。

    Method and apparatus for performing multiply operation of floating point data in 2-cycle pipeline scheme
    6.
    发明授权
    Method and apparatus for performing multiply operation of floating point data in 2-cycle pipeline scheme 失效
    在2循环流水线方案中执行浮点数据的多重运算的方法和装置

    公开(公告)号：US6144979A

    公开(公告)日：2000-11-07

    申请号：US82586

    申请日：1998-04-21

    申请人： Yoon Seok Song ,  Dong Bum Koh

    发明人： Yoon Seok Song ,  Dong Bum Koh

    IPC分类号： G06F7/44 ,  G06F7/52 ,  G06F7/38

    CPC分类号： G06F7/5338 ,  G06F7/4876

    摘要： The present invention provides a method and an apparatus for performing multiply operation of floating point data in 2-cycle pipeline scheme, which can be applied to pipelined data path so that it is always capable of processing floating point data as long as the data is not contiguous, for reducing the area of the multiplier by reducing the number of basic cells used to 1/3 of that of basic cells used in conventional techniques. The present invention for multiplying floating point data includes the steps of: (a) receiving multiplier data and multiplicand data from pipelined input in the first cycle of multiply operation; (b) generating a partial product by means of the multiplier data and multiplicand data, and generating a first sum and a first carry by adding the partial product through an adding tree circuit; and (c) generating an output of the multiply operation by adding a second sum and a second carry to the first sum and the first carry, wherein the second sum and the second carry are generated by feedbacking the first sum and the first carry in the second cycle of the multiply operation which succeeds the first cycle.

    摘要翻译： 本发明提供了一种用于在2循环流水线方案中执行浮点数据的多重运算的方法和装置，其可以应用于流水线数据路径，使得它总是能够处理浮点数据，只要该数据不是 通过减少用于+ E的碱性细胞的数量来减少乘数的面积，fra 1/3 + EE是常规技术中使用的基本细胞的面积。 用于乘以浮点数据的本发明包括以下步骤：（a）在第一乘法运算循环中从流水线输入接收乘法器数据和被乘数数据; （b）通过乘法器数据和被乘数数据产生部分积，并通过加法树电路相加产生第一和和第一进位; 以及（c）通过向第一和和第一进位添加第二和和第二进位来产生乘法运算的输出，其中通过反馈第一和和第一进位来产生第二和和第二进位 乘法运算的第二个周期成功的第一个周期。

    Apparatus for minimizing a clock skew occurring in a semiconductor device
    7.
    发明授权
    Apparatus for minimizing a clock skew occurring in a semiconductor device 失效
    用于最小化发生在半导体器件中的时钟偏移的装置

    公开(公告)号：US06081148A

    公开(公告)日：2000-06-27

    申请号：US104541

    申请日：1998-06-26

    申请人： Yoon Seok Song

    发明人： Yoon Seok Song

    IPC分类号： G06F1/04 ,  G06F1/10 ,  H03K5/13 ,  H03K5/15 ,  H03K5/14

    CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K5/15013

    摘要： A clock circuit is used in a semiconductor device having a control block and a macroblock in order to provide synchronous clocks. The clock circuit contains a clock source for generating the clocks; a clock tree, coupled between the clock source and the control block and the macroblock, for relaying the clocks to the control block and the macrobock; and programmable delays coupled between the clock source and the clock tree and between the clock tree and the control block and the macroblock in order to reduce overall clock skew.

    摘要翻译： 在具有控制块和宏块的半导体器件中使用时钟电路以提供同步时钟。 时钟电路包含用于产生时钟的时钟源; 时钟树，其耦合在时钟源与控制块和宏块之间，用于将时钟传送到控制块和宏单元; 以及可编程延迟，其耦合在时钟源和时钟树之间以及时钟树与控制块和宏块之间，以便减少总体时钟偏移。

    Thiazole compound and a process thereof
    8.
    发明授权
    Thiazole compound and a process thereof 失效
    噻唑化合物及其工艺

    公开(公告)号：US06277996B1

    公开(公告)日：2001-08-21

    申请号：US09564979

    申请日：2000-05-04

    申请人： Dae-chul Yoon ,  Seung-won Yoo ,  Dong Gyun Shin ,  Myoung Ki Lee ,  Mi Soon Park ,  Yoon Seok Lee ,  Yoon Seok Song

    发明人： Dae-chul Yoon ,  Seung-won Yoo ,  Dong Gyun Shin ,  Myoung Ki Lee ,  Mi Soon Park ,  Yoon Seok Lee ,  Yoon Seok Song

    IPC分类号： C07D27738

    CPC分类号： C07D277/40 ,  Y02P20/55

    摘要： The present invention relates to a new crystalline aminothiazole derivative represented by the following formula (I) which is very useful for the preparation of cephalosporin antibiotics, including ceftazidime and cefixime, etc: wherein R1 and R2 are the same or different and independently represent H, an alkyl group of 1 to 4 carbon atoms, or a cycloalkyl group of 3 to 5 carbon atoms, X represents chlorine or bromine, and the acid in the acid addition salt represents an inorganic acid, such as hydrochloric acid, hydrobromic acid, sulfuric acid, or perchloric acid, or an organic acid, such as formic acid, acetic acid, trifluoroacetic acid, propionic acid, methanesulfonic acid, or benzenesulfonic acid.

    摘要翻译： 本发明涉及一种非常适用于头孢菌素和头孢克肟等头孢菌素抗生素非常有用的新型结晶氨基噻唑衍生物，其中R1和R2相同或不同，独立地代表H， 1〜4个碳原子的烷基或3〜5个碳原子的环烷基，X表示氯或溴，酸加成盐中的酸表示无机酸，如盐酸，氢溴酸，硫酸 或高氯酸，或有机酸如甲酸，乙酸，三氟乙酸，丙酸，甲磺酸或苯磺酸。

    Apparatus for executing a load instruction or exchange instruction in parallel with other instructions in a dual pipelined processor
    9.
    发明授权
    Apparatus for executing a load instruction or exchange instruction in parallel with other instructions in a dual pipelined processor 失效
    用于与双流水线处理器中的其它指令并行地执行加载指令或交换指令的装置

    公开(公告)号：US6079011A

    公开(公告)日：2000-06-20

    申请号：US964113

    申请日：1997-11-05

    申请人： Yoon Seok Song

    发明人： Yoon Seok Song

    IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38

    CPC分类号： G06F9/30043 ,  G06F9/30032 ,  G06F9/30134 ,  G06F9/30163 ,  G06F9/38

    摘要： An apparatus having a stack-top updating unit for processing an exchange instruction and a load instruction in parallel in a pipe-lined processor having a stack register file. Based on an information signal representing a modification of the stack-top after the current instruction is executed in a first pipe-line, a control signal indicating that a load instruction is executed by one of the first and second pipe-lines, and a second pipe-line enable signal, the stack-top updating unit generates a new stack-top signal and a current stack-top signal. The first pipe-line, in response to the current stack-top signal and operands, executes the operands, and the second pipe-line, in response to the new stack-top signal and the control signal, performs the load instruction or an exchange instruction. As a result, the load instruction or the Fload instruction can be simultaneously executed with another instruction or operand in the pipe-lined processor in an effective manner.

    摘要翻译： 一种具有堆叠顶部更新单元的装置，用于在具有堆栈寄存器文件的管道内处理器中并行地处理交换指令和加载指令。 基于表示在第一管线中执行当前指令之后的堆叠顶部的修改的信息信号，指示由第一和第二管线之一执行加载指令的控制信号，以及第二管线 管线使能信号，堆叠顶部更新单元生成新的堆栈顶部信号和当前堆叠顶部信号。 响应于当前栈顶信号和操作数，第一管线响应于新的堆顶信号和控制信号执行操作数，第二管线执行加载指令或交换 指令。 因此，加载指令或Fload指令可以以有效的方式与管道内置处理器中的另一个指令或操作数同时执行。

    Process for preparing cephalosporin antibiotics using new thiazole compound
    10.
    发明授权
    Process for preparing cephalosporin antibiotics using new thiazole compound 失效
    使用新的噻唑化合物制备头孢菌素抗生素的方法

    公开(公告)号：US06384212B1

    公开(公告)日：2002-05-07

    申请号：US09564980

    申请日：2000-05-04

    申请人： Dae-chul Yoon ,  Seung Won Yoo ,  Dong Gyun Shin ,  Myoung Ki Lee ,  Mi Soon Park ,  Yoon Seok Lee ,  Yoon Seok Song ,  Ju Cheol Lee ,  Sang Mi Oh

    发明人： Dae-chul Yoon ,  Seung Won Yoo ,  Dong Gyun Shin ,  Myoung Ki Lee ,  Mi Soon Park ,  Yoon Seok Lee ,  Yoon Seok Song ,  Ju Cheol Lee ,  Sang Mi Oh

    IPC分类号： C07D50124

    CPC分类号： C07D501/00

    摘要： The present invention relates to a new, simple, and easy process for preparing cephalosporin antibiotics of the following formula (I), such as ceftazidime and cefixime. The process comprises acylating a 7-amino cephalosporanic acid derivative of the following formula (III) with a crystalline aminothiazole compound of the following formula (II): wherein R1 and R2 are the same or different and independently represent H, a C1-4 alkyl or C3-5 cycloalkyl group, R4 represents acetoxymethyl, methylpyridine, or vinyl, X represents chlorine or bromine, and the acid in the acid addition salt represents an inorganic acid, such as hydrochloric acid, or an organic acid, such as formic acid or acetic acid.

    摘要翻译： 本发明涉及用于制备下列通式（I）的头孢菌素抗生素的新的，简单的和容易的方法，例如头孢他啶和头孢克肟。 该方法包括用下式（II）的结晶氨基噻唑化合物酰化下式（III）的7-氨基头孢菌酸衍生物：其中R 1和R 2相同或不同并且独立地代表H，C 1-4烷基 或C3-5环烷基，R4表示乙酰氧基甲基，甲基吡啶或乙烯基，X表示氯或溴，酸加成盐中的酸表示无机酸，如盐酸或有机酸，如甲酸或 醋酸。