公开(公告)号：US07231336B2

公开(公告)日：2007-06-12

申请号：US10729785

申请日：2003-12-05

申请人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

发明人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.

摘要翻译： 根据本发明，提供了一种在模拟电路中进行毛刺检查的方法。 确定电路优化参数的当前最大值和最小值。 接下来，基于最大和最小优化参数来确定用于电路仿真的信号脉冲特性。 根据当前的最大和最小优化参数确定当前的平均优化参数。 基于优化参数和信号脉冲特征值计算质量标准参数。 如果主标准参数收敛到指定范围内，则电路仿真的测量结果将被解析并报告为最终。 如果主标准参数不收敛，则该过程通过重新计算优化参数继续，直到主标准参数收敛。

公开(公告)号：US20050049846A1

公开(公告)日：2005-03-03

申请号：US10729596

申请日：2003-12-05

申请人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

发明人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/08

摘要： There is provided a method of performing a timing soft error check on a simulated circuit. The method comprises creating a critical-path circuit or using a full-chip circuit to be analyzed of the circuit. Next, the circuit is simulated based on an initial minimum optimization parameter and an initial maximum optimization parameter. A maximum and minimum primary criterion parameter are calculated for each of the minimum and maximum optimization parameters. If the minimum and maximum optimization parameters do not indicate the same status (i.e., both succeed or both fail), then a new current optimization parameter is determined. The circuit is then simulated using the new current optimization parameter. If the simulation is successful, then a timing soft error check is performed. If the simulation is not successful, then it is determined if the primary criterion parameter is converging. If the primary criterion parameter is not converging, then the current optimization parameter is set to a new value.

摘要翻译： 提供了对模拟电路执行定时软错误检查的方法。 该方法包括创建一个关键路径电路或使用全芯片电路进行电路分析。 接下来，基于初始最小优化参数和初始最大优化参数来模拟电路。 针对每个最小和最大优化参数计算最大和最小主标准参数。 如果最小和最大优化参数不指示相同的状态（即，成功还是同时失败），则确定新的当前优化参数。 然后使用新的当前优化参数模拟电路。 如果模拟成功，则执行定时软错误检查。 如果模拟不成功，则确定主标准参数是否收敛。 如果主标准参数不收敛，则将当前优化参数设置为新值。

公开(公告)号：US20050049845A1

公开(公告)日：2005-03-03

申请号：US10729701

申请日：2003-12-05

申请人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

发明人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： In accordance with the present invention there is provided a method of simulating a memory circuit design in order to verify the signal strength of bit lines. The method begins by identifying circuit elements of the memory circuit design. Next, a memory circuit path is extracted from the circuit elements. The memory circuit is simulated and the maximum voltage difference between bit lines is measured. The maximum voltage difference is measured to a noise margin in order to verify the signal strength of the bit lines.

摘要翻译： 根据本发明，提供了一种模拟存储器电路设计以验证位线的信号强度的方法。 该方法从识别存储器电路设计的电路元件开始。 接下来，从电路元件提取存储器电路路径。 模拟存储器电路，测量位线之间的最大电压差。 为了验证位线的信号强度，将最大电压差测量为噪声容限。

公开(公告)号：US20050050498A1

公开(公告)日：2005-03-03

申请号：US10729697

申请日：2003-12-05

申请人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

发明人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5045

摘要： In accordance with the present invention there is provided a method for determining an optimized parameter for a circuit simulation. A circuit path for the simulation is determined, and maximum and minimum optimization parameters are decided. Next, the circuit path is simulated using the maximum optimization parameter. The circuit path is simulated using the minimum optimization parameter and a primary criteria parameter is also calculated. The simulations are compared to determine whether the same status (both succeed or both fail) is generated for both the minimum optimization parameter and the maximum optimization parameter. If the simulations do not indicate the same status, then the optimization parameter is recalculated and the circuit is simulated until the primary criteria parameter converges to a prescribed value.

摘要翻译： 根据本发明，提供了一种用于确定用于电路仿真的优化参数的方法。 确定用于模拟的电路路径，并且确定最大和最小优化参数。 接下来，使用最大优化参数模拟电路路径。 使用最小优化参数模拟电路路径，并计算主要准则参数。 比较模拟以确定最小优化参数和最大优化参数是否生成相同的状态（均为成功或同时失败）。 如果模拟没有指示相同的状态，则重新计算优化参数，并模拟电路，直到主标准参数收敛到规定值。

公开(公告)号：US06249901B1

公开(公告)日：2001-06-19

申请号：US09564235

申请日：2000-05-04

申请人： Chen-Ping Yuan ,  Hung-Ta Wei ,  You-Pang Wei

发明人： Chen-Ping Yuan ,  Hung-Ta Wei ,  You-Pang Wei

IPC分类号： G06F1716

CPC分类号： G06F17/5022

摘要： An automatic memory characterization system for determining timing characteristics associated with each of a plurality of circuit instances of a memory compiler circuit design includes: an automatic circuit reduction tool for receiving a circuit netlist extracted from layout data defining a circuit instance of the memory compiler, and for generating a critical path netlist; a memory storage unit for storing a timing parameter database including a script file having memory characterization instructions, and at least one specification file associated with one of the timing characteristics to be characterized for the circuit instance, the specification file having a plurality of input signal parameters defining a plurality of input signals to be applied to selected input nodes of the circuit instance, and a plurality of output loading parameters defining a plurality of output loads to be applied to selected output nodes of the circuit instance; a stimulus generator responsive to the input signal parameters and operative to generate a stimulus file; and a circuit simulation manager operative to access the timing parameter database, and to execute at least a portion of the memory characterization instructions, and to generate an updated critical path netlist based on the output loading parameters, the updated critical path netlist and the stimulus file being adapted for use in simulation of the circuit instance.

摘要翻译： 用于确定与存储器编译器电路设计的多个电路实例中的每一个相关联的定时特性的自动存储器表征系统包括：自动电路简化工具，用于接收从定义存储器编译器的电路实例的布局数据中提取的电路网表;以及 用于生成关键路径网表; 存储器存储单元，用于存储包括具有存储器表征指令的脚本文件的定时参数数据库，以及与用于电路实例表征的定时特性之一相关联的至少一个规范文件，所述规范文件具有多个输入信号参数 定义要应用于所述电路实例的选定输入节点的多个输入信号;以及多个输出加载参数，其定义要应用于所述电路实例的选定输出节点的多个输出负载; 响应于所述输入信号参数并且可操作地产生刺激文件的刺激发生器; 以及电路仿真管理器，用于访问所述定时参数数据库，并且执行所述存储器表征指令的至少一部分，并且基于所述输出加载参数，所述更新的关键路径网表和所述刺激文件来生成更新的关键路径网表 适用于仿真电路实例。

公开(公告)号：US07203918B2

公开(公告)日：2007-04-10

申请号：US10981803

申请日：2004-11-04

申请人： You-Pang Wei ,  George (Yuhung) Liao ,  Mickie (Mingchi) Liu ,  Yu-Jiao Ping

发明人： You-Pang Wei ,  George (Yuhung) Liao ,  Mickie (Mingchi) Liu ,  Yu-Jiao Ping

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for performing a signal integrity and delay check for circuit simulations is disclosed. Nodes of the circuit are selected and an optimization parameter is determined. The optimization parameter may be either the setup or hold time for the circuit simulation. The current optimization parameter is determined to be the average of the current minimum and maximum optimization parameters. A primary criteria is calculated in response to the optimization parameters. The primary criteria may be a bisection error of the circuit simulation. If the primary criteria converges to a prescribed range, then the measurement results from the simulation are parsed. If the primary criteria does not converge, then the circuit is simulated using the current optimization parameter. For a signal integrity check, switch difference errors are identified and used to set a new optimization parameter. For a delay check, delay difference errors are identified and used to set a new optimization parameter. The method of this signal integrity and delay check can be applied to semiconductor IPs (Intellectual Property) including cell, I/O and memory circuit characterization and verification.

摘要翻译： 公开了一种用于执行电路模拟的信号完整性和延迟检查的方法。 选择电路的节点并确定优化参数。 优化参数可以是电路仿真的设置或保持时间。 当前优化参数被确定为当前最小和最大优化参数的平均值。 根据优化参数计算主要标准。 主要标准可能是电路仿真的二分误差。 如果主要标准收敛于规定范围，则解析模拟的测量结果。 如果主要标准不收敛，则使用当前优化参数来模拟电路。 对于信号完整性检查，识别开关差异误差并用于设置新的优化参数。 对于延迟检查，识别延迟差异误差并用于设置新的优化参数。 该信号完整性和延迟检查的方法可以应用于包括单元，I / O和存储器电路表征和验证的半导体IP（知识产权）。

公开(公告)号：US07131088B2

公开(公告)日：2006-10-31

申请号：US10729697

申请日：2003-12-05

申请人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

发明人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036 ,  G06F17/5045

摘要： In accordance with the present invention there is provided a method for determining an optimized parameter for a circuit simulation. A circuit path for the simulation is determined, and maximum and minimum optimization parameters are decided. Next, the circuit path is simulated using the maximum optimization parameter. The circuit path is simulated using the minimum optimization parameter and a primary criteria parameter is also calculated. The simulations are compared to determine whether the same status (both succeed or both fail) is generated for both the minimum optimization parameter and the maximum optimization parameter. If the simulations do not indicate the same status, then the optimization parameter is recalculated and the circuit is simulated until the primary criteria parameter converges to a prescribed value.

摘要翻译： 根据本发明，提供了一种用于确定用于电路仿真的优化参数的方法。 确定用于模拟的电路路径，并且确定最大和最小优化参数。 接下来，使用最大优化参数模拟电路路径。 使用最小优化参数模拟电路路径，并计算主要准则参数。 比较模拟以确定最小优化参数和最大优化参数是否生成相同的状态（均为成功或同时失败）。 如果模拟没有指示相同的状态，则重新计算优化参数，并模拟电路，直到主标准参数收敛到规定值。

公开(公告)号：US20050120317A1

公开(公告)日：2005-06-02

申请号：US10981803

申请日：2004-11-04

申请人： You-Pang Wei ,  George (Yuhung) Liao ,  Mickie (Mingchi) Liu ,  Yu-Jiao Ping

发明人： You-Pang Wei ,  George (Yuhung) Liao ,  Mickie (Mingchi) Liu ,  Yu-Jiao Ping

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5022

摘要： A method for performing a signal integrity and delay check for circuit simulations is disclosed. Nodes of the circuit are selected and an optimization parameter is determined. The optimization parameter may be either the setup or hold time for the circuit simulation. The current optimization parameter is determined to be the average of the current minimum and maximum optimization parameters. A primary criteria is calculated in response to the optimization parameters. The primary criteria may be a bisection error of the circuit simulation. If the primary criteria converges to a prescribed range, then the measurement results from the simulation are parsed. If the primary criteria does not converge, then the circuit is simulated using the current optimization parameter. For a signal integrity check, switch difference errors are identified and used to set a new optimization parameter. For a delay check, delay difference errors are identified and used to set a new optimization parameter. The method of this signal integrity and delay check can be applied to semiconductor IPs (Intellectual Property) including cell, I/O and memory circuit characterization and verification.

摘要翻译： 公开了一种用于执行电路模拟的信号完整性和延迟检查的方法。 选择电路的节点并确定优化参数。 优化参数可以是电路仿真的设置或保持时间。 当前优化参数被确定为当前最小和最大优化参数的平均值。 根据优化参数计算主要标准。 主要标准可能是电路仿真的二分误差。 如果主要标准收敛于规定范围，则解析模拟的测量结果。 如果主要标准不收敛，则使用当前优化参数来模拟电路。 对于信号完整性检查，识别开关差异误差并用于设置新的优化参数。 对于延迟检查，识别延迟差异误差并用于设置新的优化参数。 该信号完整性和延迟检查的方法可以应用于包括单元，I / O和存储器电路表征和验证的半导体IP（知识产权）。

公开(公告)号：US20050049844A1

公开(公告)日：2005-03-03

申请号：US10729785

申请日：2003-12-05

申请人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

发明人： You-Pang Wei ,  Yuhung Liao ,  Mingchi Liu ,  YuJiao Ping

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In accordance with the present invention there is provided a method for performing a glitch check in simulating a circuit. Current maximum and minimum values for optimization parameters of the circuit are determined. Next, a signal pulse characteristic for the circuit simulation is determined based on the maximum and minimum optimization parameters. A current averaged optimization parameter is determined from the current maximum and minimum optimization parameters. A prime criterion parameter is calculated based on the optimization parameters and the signal pulse characteristic value. If the prime criterion parameter converges into a specified range then measurement results from the circuit simulation are parsed and reported as final. If the prime criterion parameter does not converge, then the process continues by recalculating the optimization parameters until the prime criterion parameter converges.

摘要翻译： 根据本发明，提供了一种在模拟电路中进行毛刺检查的方法。 确定电路优化参数的当前最大值和最小值。 接下来，基于最大和最小优化参数来确定用于电路仿真的信号脉冲特性。 根据当前的最大和最小优化参数确定当前的平均优化参数。 基于优化参数和信号脉冲特征值计算质量标准参数。 如果主标准参数收敛到指定范围内，则电路仿真的测量结果将被解析并报告为最终。 如果主标准参数不收敛，则该过程通过重新计算优化参数继续，直到主标准参数收敛。

公开(公告)号：US06289412B1

公开(公告)日：2001-09-11

申请号：US09267333

申请日：1999-03-12

申请人： Chen-Ping Yuan ,  Che-Cheng Lin ,  You-Pang Wei

发明人： Chen-Ping Yuan ,  Che-Cheng Lin ,  You-Pang Wei

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F17/5081

摘要： A process is provided for generating a synoptic layout database for efficient layout parasitic extraction and circuit simulation in post-layout verification of an integrated circuit (IC) design for a system having a plurality of repetitive subcircuits. The process includes the steps of: receiving an input layout database including a plurality of geometric objects including cells representing the IC design, each of the cells including a plurality of polygons; identifying a plurality of repetitive cells of the input layout database, the repetitive cells being associated with the repetitive sub-circuits; recognizing at least one pattern of the repetitive cells; defining at least one cut region of the input layout database, the cut region being defined by physical layout coordinates, the cut region intersecting a corresponding pattern of the repetitive cells; and generating a synoptic layout database.

摘要翻译： 提供了一种用于生成用于具有多个重复子电路的系统的集成电路（IC）设计的布局后验证中的有效布局寄生提取和电路模拟的概要布局数据库的过程。 该过程包括以下步骤：接收包括包括表示IC设计的单元的多个几何对象的输入布局数据库，每个单元包括多个多边形; 识别所述输入布局数据库的多个重复单元，所述重复单元与所述重复子电路相关联; 识别重复细胞的至少一种模式; 限定输入布局数据库的至少一个切割区域，切割区域由物理布局坐标定义，切割区域与重复单元格的相应图案相交; 并生成概要布局数据库。