公开(公告)号：US20120241969A1

公开(公告)日：2012-09-27

申请号：US13240054

申请日：2011-09-22

申请人： Mitsuru OKAZAKI ,  Youichi KAJIWARA ,  Naoki TAKAHASHI ,  Akira SHIMIZU

发明人： Mitsuru OKAZAKI ,  Youichi KAJIWARA ,  Naoki TAKAHASHI ,  Akira SHIMIZU

IPC分类号： H01L23/50

CPC分类号： H01L29/0603 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

摘要翻译： 半导体集成电路器件包括：矩形半导体衬底; 形成在所述半导体衬底上或之上的金属布线层; 以及覆盖金属布线层的钝化层。 在半导体基板的角部设置没有形成金属布线层的部分的角部非布线区域。 在金属布线层的靠近半导体基板的角部的部分形成狭缝。 钝化层包括形成在金属布线层上的第一钝化层和形成在第一钝化层上的第二钝化层。 第一钝化层由比第二钝化层的材料软的材料形成。

公开(公告)号：US20080253047A1

公开(公告)日：2008-10-16

申请号：US11597980

申请日：2005-05-23

申请人： Hirotaka Takihara ,  Youichi Kajiwara ,  Masanori Tsuchihashi

发明人： Hirotaka Takihara ,  Youichi Kajiwara ,  Masanori Tsuchihashi

IPC分类号： H02H9/02

CPC分类号： H03K17/0822 ,  H01L27/0248 ,  H01L2224/48091 ,  H01L2924/00014

摘要： In a semiconductor device, a problem of heat generation and power loss is alleviated, and the semiconductor device is protected against the failure due to the overcurrent. The semiconductor device includes an IC chip having a large-current output. In the IC chip a measuring terminal is electrically connected with a first pad via a gold wire. A potential difference generated by the impedance of the gold wire is compared with a predetermined value. When the potential difference exceeds the predetermined threshold level, the semiconductor device operates to turn off a PMOS-type transistor.

摘要翻译： 在半导体装置中，能够减轻发热和功率损耗的问题，能够防止半导体装置因过电流导致的故障。 半导体器件包括具有大电流输出的IC芯片。 在IC芯片中，测量端子通过金线与第一焊盘电连接。 由金线的阻抗产生的电位差与预定值进行比较。 当电位差超过预定阈值电平时，半导体器件操作以关断PMOS型晶体管。

公开(公告)号：US20080129477A1

公开(公告)日：2008-06-05

申请号：US11721518

申请日：2005-11-18

申请人： Naoki Takahashi ,  Youichi Kajiwara

发明人： Naoki Takahashi ,  Youichi Kajiwara

IPC分类号： H04B1/04 ,  E05B49/00 ,  B60R25/00

CPC分类号： B60C23/0408 ,  B60C23/0433 ,  B60C23/044 ,  B60R25/245

摘要： According to the invention, a transmission device has a transmission antenna portion, an output portion that has a first switch and a second switch connected in series between two different potentials and that derives from the node between the first and second switches an output current fed to the transmission antenna portion, an output driving portion that controls turning-on and -off of the first and second switches, and duty ratio setting means for variably setting the duty ratio at which the output driving portion drives the first and second switches. The invention makes it possible to adjust the radiowave coverage area of the transmission antenna portion easily without complicated work.

摘要翻译： 根据本发明，发送装置具有发送天线部分，输出部分具有串联连接在两个不同电位之间的第一开关和第二开关，并且从第一和第二开关之间的节点导出输出电流馈送到 发送天线部分，控制第一和第二开关的导通和关闭的输出驱动部分，以及用于可变地设置输出驱动部分驱动第一和第二开关的占空比的占空比设定装置。 本发明使得可以容易地调整发射天线部分的无线电波覆盖区域而不需要复杂的工作。

公开(公告)号：US08786092B2

公开(公告)日：2014-07-22

申请号：US13240054

申请日：2011-09-22

申请人： Mitsuru Okazaki ,  Youichi Kajiwara ,  Naoki Takahashi ,  Akira Shimizu

发明人： Mitsuru Okazaki ,  Youichi Kajiwara ,  Naoki Takahashi ,  Akira Shimizu

IPC分类号： H01L23/50

CPC分类号： H01L29/0603 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

摘要翻译： 半导体集成电路器件包括：矩形半导体衬底; 形成在所述半导体衬底上或之上的金属布线层; 以及覆盖金属布线层的钝化层。 在半导体基板的角部设置没有形成金属布线层的部分的角部非布线区域。 在金属布线层的靠近半导体基板的角部的部分形成狭缝。 钝化层包括形成在金属布线层上的第一钝化层和形成在第一钝化层上的第二钝化层。 第一钝化层由比第二钝化层的材料软的材料形成。

公开(公告)号：US20090096107A1

公开(公告)日：2009-04-16

申请号：US11917186

申请日：2006-06-13

申请人： Mitsuru Okazaki ,  Youichi Kajiwara ,  Naoki Takahashi ,  Akira Shimizu

发明人： Mitsuru Okazaki ,  Youichi Kajiwara ,  Naoki Takahashi ,  Akira Shimizu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3171 ,  H01L23/562 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, an element forming region and a metal wiring layer are covered with a passivation layer on a semiconductor substrate which is cut out in a rectangular shape. At four corners of the device, the passivation layer is provided with corner non-wiring regions formed directly on the semiconductor substrate. Thus, crack generation on the passivation layer due to heat stress can be suppressed.

摘要翻译： 在半导体集成电路器件中，元件形成区域和金属布线层在被切割成矩形的半导体衬底上被钝化层覆盖。 在器件的四个角处，钝化层设置有直接形成在半导体衬底上的拐角非布线区域。 因此，可以抑制由于热应力引起的钝化层上的裂纹产生。