公开(公告)号：US08786092B2

公开(公告)日：2014-07-22

申请号：US13240054

申请日：2011-09-22

申请人： Mitsuru Okazaki ,  Youichi Kajiwara ,  Naoki Takahashi ,  Akira Shimizu

发明人： Mitsuru Okazaki ,  Youichi Kajiwara ,  Naoki Takahashi ,  Akira Shimizu

IPC分类号： H01L23/50

CPC分类号： H01L29/0603 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

摘要翻译： 半导体集成电路器件包括：矩形半导体衬底; 形成在所述半导体衬底上或之上的金属布线层; 以及覆盖金属布线层的钝化层。 在半导体基板的角部设置没有形成金属布线层的部分的角部非布线区域。 在金属布线层的靠近半导体基板的角部的部分形成狭缝。 钝化层包括形成在金属布线层上的第一钝化层和形成在第一钝化层上的第二钝化层。 第一钝化层由比第二钝化层的材料软的材料形成。

公开(公告)号：US20090096107A1

公开(公告)日：2009-04-16

申请号：US11917186

申请日：2006-06-13

申请人： Mitsuru Okazaki ,  Youichi Kajiwara ,  Naoki Takahashi ,  Akira Shimizu

发明人： Mitsuru Okazaki ,  Youichi Kajiwara ,  Naoki Takahashi ,  Akira Shimizu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3171 ,  H01L23/562 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, an element forming region and a metal wiring layer are covered with a passivation layer on a semiconductor substrate which is cut out in a rectangular shape. At four corners of the device, the passivation layer is provided with corner non-wiring regions formed directly on the semiconductor substrate. Thus, crack generation on the passivation layer due to heat stress can be suppressed.

摘要翻译： 在半导体集成电路器件中，元件形成区域和金属布线层在被切割成矩形的半导体衬底上被钝化层覆盖。 在器件的四个角处，钝化层设置有直接形成在半导体衬底上的拐角非布线区域。 因此，可以抑制由于热应力引起的钝化层上的裂纹产生。

公开(公告)号：US20090309117A1

公开(公告)日：2009-12-17

申请号：US11915921

申请日：2006-05-29

申请人： Mitsuru Okazaki ,  Naoki Takahashi ,  Akira Shimizu ,  Kenichi Nakata

发明人： Mitsuru Okazaki ,  Naoki Takahashi ,  Akira Shimizu ,  Kenichi Nakata

IPC分类号： H01L33/00 ,  H01L29/73 ,  H02H9/00

CPC分类号： H05B33/0884 ,  H01L27/0248 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/1305 ,  H01L2924/30107 ,  Y02B20/341 ,  H01L2924/00

摘要： In a protection circuit connected, via lines including an inductance component, to a circuit to be protected, a first transistor is arranged on a path to ground from a connection point of the protection circuit and the line. A second transistor is arranged on a path to ground from a connection point of the circuit to be protected and the line, and extracts, from a connection point, a current corresponding to a current flowing in the first transistor. The first and the second transistors are NPN bipolar transistors having a base and an emitter are commonly connected. A resistor is connected between the base and the emitter of the first transistor, and a diode is connected between the base and a collector.

摘要翻译： 在通过包括电感分量的线路连接到保护电路的保护电路中，第一晶体管被布置在从保护电路和线路的连接点到达的路径上。 第二晶体管被布置在从被保护电路的连接点到线路的路径上，并从连接点提取与流过第一晶体管的电流相对应的电流。 第一和第二晶体管是具有基极和发射极共同连接的NPN双极晶体管。 电阻器连接在第一晶体管的基极和发射极之间，二极管连接在基极和集电极之间。

公开(公告)号：US07889467B2

公开(公告)日：2011-02-15

申请号：US11915921

申请日：2006-05-29

申请人： Mitsuru Okazaki ,  Naoki Takahashi ,  Akira Shimizu ,  Kenichi Nakata

发明人： Mitsuru Okazaki ,  Naoki Takahashi ,  Akira Shimizu ,  Kenichi Nakata

IPC分类号： H02H9/00

CPC分类号： H05B33/0884 ,  H01L27/0248 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/1305 ,  H01L2924/30107 ,  Y02B20/341 ,  H01L2924/00

摘要： In a protection circuit connected, via lines including an inductance component, to a circuit to be protected, a first transistor is arranged on a path to ground from a connection point of the protection circuit and the line. A second transistor is arranged on a path to ground from a connection point of the circuit to be protected and the line, and extracts, from a connection point, a current corresponding to a current flowing in the first transistor. The first and the second transistors are NPN bipolar transistors having a base and an emitter are commonly connected. A resistor is connected between the base and the emitter of the first transistor, and a diode is connected between the base and a collector.

摘要翻译： 在通过包括电感分量的线路连接到保护电路的保护电路中，第一晶体管被布置在从保护电路和线路的连接点到达的路径上。 第二晶体管被布置在从被保护电路的连接点到线路的路径上，并从连接点提取与流过第一晶体管的电流相对应的电流。 第一和第二晶体管是具有基极和发射极共同连接的NPN双极晶体管。 电阻器连接在第一晶体管的基极和发射极之间，二极管连接在基极和集电极之间。