公开(公告)号：US20120115298A1

公开(公告)日：2012-05-10

申请号：US13238330

申请日：2011-09-21

申请人： Jong-Pil KIM ,  Young-Goan JANG ,  Dong-Won KIM ,  Hag-Ju CHO

发明人： Jong-Pil KIM ,  Young-Goan JANG ,  Dong-Won KIM ,  Hag-Ju CHO

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28008 ,  H01L21/28123 ,  H01L21/76 ,  H01L21/76232 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

摘要： A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

摘要翻译： 制造栅极的方法包括在基板的基本上整个表面上依次形成绝缘层和导电层。 衬底在其中具有器件隔离层，器件隔离层的顶表面高于衬底的顶表面。 该方法包括通过图案化绝缘层和导电层来平坦化导电层的顶表面并形成栅电极。

公开(公告)号：US07132331B2

公开(公告)日：2006-11-07

申请号：US10990903

申请日：2004-11-17

申请人： Young-Goan Jang ,  Chang-Hyun Lee ,  Jae-Hoon Kim

发明人： Young-Goan Jang ,  Chang-Hyun Lee ,  Jae-Hoon Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/115

摘要： A semiconductor device having a self-aligned gate conductive layer and a method of fabricating the same are disclosed. In embodiments of the present invention, a plurality of field isolation patterns are formed on a semiconductor substrate to define a plurality of active regions in the semiconductor substrate. The density of the field isolation patterns is then increased by, for example, a thermal annealing process. A plurality of gate insulation patterns are then formed on respective of the active regions. A plurality of first conductive patterns are then formed on respective of the gate insulation patterns.

摘要翻译： 公开了具有自对准栅极导电层的半导体器件及其制造方法。 在本发明的实施例中，在半导体衬底上形成多个场隔离图案以在半导体衬底中限定多个有源区。 然后通过例如热退火工艺增加场隔离图案的密度。 然后在相应的有源区上形成多个栅极绝缘图案。 然后在相应的栅极绝缘图案上形成多个第一导电图案。

公开(公告)号：US20050136601A1

公开(公告)日：2005-06-23

申请号：US10990903

申请日：2004-11-17

申请人： Young-Goan Jang ,  Chang-Hyun Lee ,  Jae-Hoon Kim

发明人： Young-Goan Jang ,  Chang-Hyun Lee ,  Jae-Hoon Kim

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/115

摘要： A semiconductor device having a self-aligned gate conductive layer and a method of fabricating the same are disclosed. In embodiments of the present invention, a plurality of field isolation patterns are formed on a semiconductor substrate to define a plurality of active regions in the semiconductor substrate. The density of the field isolation patterns is then increased by, for example, a thermal annealing process. A plurality of gate insulation patterns are then formed on respective of the active regions. A plurality of first conductive patterns are then formed on respective of the gate insulation patterns.

摘要翻译： 公开了具有自对准栅极导电层的半导体器件及其制造方法。 在本发明的实施例中，在半导体衬底上形成多个场隔离图案以在半导体衬底中限定多个有源区。 然后通过例如热退火工艺增加场隔离图案的密度。 然后在相应的有源区上形成多个栅极绝缘图案。 然后在相应的栅极绝缘图案上形成多个第一导电图案。

公开(公告)号：US06423654B1

公开(公告)日：2002-07-23

申请号：US09499955

申请日：2000-02-08

申请人： Sung-Min Sim ,  Young-Goan Jang

发明人： Sung-Min Sim ,  Young-Goan Jang

IPC分类号： H01L21469

CPC分类号： H01L21/76801 ,  C23C16/308 ,  H01L21/3145 ,  Y10S438/909

摘要： There is provided a semiconductor device having a silicon oxynitride passivation layer and a fabrication method thereof. The passivation layer is formed of a silicon oxynitride having a dielectric constant of 5.0-6.0 and an atomic composition ratio of silicon (25-40%), oxygen (25-40%), and nitrogen (25-40%). Therefore, the passivation layer has a low dielectric constant and is highly moisture-resistant to thereby reduce the parasitic capacitance between metal wiring layers.

摘要翻译： 提供了具有氮氧化硅钝化层的半导体器件及其制造方法。 钝化层由介电常数为5.0-6.0，硅（25-40％），氧（25-40％）和氮（25-40％）的原子组成比的氮氧化硅形成。 因此，钝化层的介电常数低，耐湿度高，从而降低金属布线层之间的寄生电容。

公开(公告)号：US08501550B2

公开(公告)日：2013-08-06

申请号：US13238330

申请日：2011-09-21

申请人： Jong-Pil Kim ,  Young-Goan Jang ,  Dong-Won Kim ,  Hag-Ju Cho

发明人： Jong-Pil Kim ,  Young-Goan Jang ,  Dong-Won Kim ,  Hag-Ju Cho

IPC分类号： H01L21/335 ,  H01L21/8232

CPC分类号： H01L21/28008 ,  H01L21/28123 ,  H01L21/76 ,  H01L21/76232 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

摘要： A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

摘要翻译： 制造栅极的方法包括在基板的基本上整个表面上依次形成绝缘层和导电层。 衬底在其中具有器件隔离层，器件隔离层的顶表面高于衬底的顶表面。 该方法包括通过图案化绝缘层和导电层来平坦化导电层的顶表面并形成栅电极。