公开(公告)号：US20060184903A1

公开(公告)日：2006-08-17

申请号：US11398609

申请日：2006-04-06

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

公开(公告)号：US07337414B2

公开(公告)日：2008-02-26

申请号：US11398609

申请日：2006-04-06

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

公开(公告)号：US20070028203A1

公开(公告)日：2007-02-01

申请号：US11258176

申请日：2005-10-26

申请人： Mitsuru Sato ,  Hiroji Takeyama ,  Yuki Kumon ,  Tomoki Kanemochi

发明人： Mitsuru Sato ,  Hiroji Takeyama ,  Yuki Kumon ,  Tomoki Kanemochi

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： To create a function verification description, which is used for verifying a result of simulation performed on a finite state machine, irrespective of description languages of designing an FSM and creating the function verification description even by a person without knowledge of the language and the creation method of the function verification description, there is provided an apparatus including: an extracting section for extracting data concerning a performance that is a subject for the simulation from specification data of the FSM; a retaining section for retaining one or more description templates for function verification descriptions which are associated with one or more performances that are subjects for simulation; a selecting section for selecting a description template corresponding to the first performance; and a creating section for creating the function verifying description by substituting the data concerning the first performance into the particular description template selected.

摘要翻译： 为了创建功能验证描述，用于验证在有限状态机上执行的模拟结果，而不管设计FSM的描述语言以及甚至由没有语言知识的人创建功能验证描述和创建方法 提供了一种装置，包括：提取部分，用于从FSM的指定数据中提取与模拟对象的性能有关的数据; 一个保留部分，用于保存与作为模拟对象的一个​​或多个演奏相关联的功能验证描述的一个或多个描述模板; 选择部分，用于选择与第一演奏相对应的描述模板; 以及创建部分，用于通过将关于第一表演的数据替换到所选择的特定描述模板中来创建功能验证描述。

公开(公告)号：US07143375B2

公开(公告)日：2006-11-28

申请号：US10705787

申请日：2003-11-12

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

公开(公告)号：US20060047451A1

公开(公告)日：2006-03-02

申请号：US11022969

申请日：2004-12-28

申请人： Mituru Sato ,  Yuki Kumon ,  Hiroji Takeyama ,  Terunobu Maruyama ,  Miki Takagi ,  Tomoki Kanemochi

发明人： Mituru Sato ,  Yuki Kumon ,  Hiroji Takeyama ,  Terunobu Maruyama ,  Miki Takagi ,  Tomoki Kanemochi

IPC分类号： G01R13/00

CPC分类号： G06F17/5045

摘要： A circuit diagram display apparatus displays a plurality of logic circuit diagrams. An associating unit associates the logic circuits based on at least any one of identification information, structural information, logical equivalence information, and external designated information about the logic circuits. A display format changing unit changes a display format between a side-by-side format and one-below-the-other format. A display controller performs control to display a target point in the logic circuit diagram in the same position before and after the display format is changed.

摘要翻译： 电路图显示装置显示多个逻辑电路图。 关联单元基于识别信息，结构信息，逻辑等价信息和关于逻辑电路的外部指定信息中的至少一个来关联逻辑电路。 显示格式改变单元改变并排格式和一种在另一种格式之间的显示格式。 显示控制器执行控制以在显示格式改变之前和之后在相同位置显示逻辑电路图中的目标点。