公开(公告)号：US07337414B2

公开(公告)日：2008-02-26

申请号：US11398609

申请日：2006-04-06

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

公开(公告)号：US20060184903A1

公开(公告)日：2006-08-17

申请号：US11398609

申请日：2006-04-06

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

公开(公告)号：US07143375B2

公开(公告)日：2006-11-28

申请号：US10705787

申请日：2003-11-12

申请人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

发明人： Terunobu Maruyama ,  Hiroji Takeyama ,  Takeo Nakamura ,  Mitsuru Satou ,  Yuki Kumon ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing section 7 performs structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DB 5 records the results of the structural matching as an identifier for each element. A subcone extracting section 8 extracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying section 9 performs logical equivalence verification between the two circuits for each of the extracted subcones. A display control section 10 displays only those subcones for which the logical equivalence verification has resulted in mismatch.

摘要翻译： 可以减少逻辑等价验证后不匹配原因分析的时间和麻烦，可以缩短设计和验证TAT。 逻辑等价验证装置在两个电路之间执行逻辑等价验证，并显示逻辑等效验证的结果。 预处理部7执行结构匹配，以便确定在两个电路的相应逻辑锥中是否存在与电路结构相对应的部分。 内部DB 5将结构匹配的结果记录为每个元素的标识符。 子提取部分8从每个逻辑锥体中提取彼此相互并且具有相同标识符的元素集合作为子单元。 验证部分9对于每个提取的子晶体执行两个电路之间的逻辑等价性验证。 显示控制部10仅显示逻辑等同性验证导致不匹配的那些子会话。

公开(公告)号：US20060047451A1

公开(公告)日：2006-03-02

申请号：US11022969

申请日：2004-12-28

申请人： Mituru Sato ,  Yuki Kumon ,  Hiroji Takeyama ,  Terunobu Maruyama ,  Miki Takagi ,  Tomoki Kanemochi

发明人： Mituru Sato ,  Yuki Kumon ,  Hiroji Takeyama ,  Terunobu Maruyama ,  Miki Takagi ,  Tomoki Kanemochi

IPC分类号： G01R13/00

CPC分类号： G06F17/5045

摘要： A circuit diagram display apparatus displays a plurality of logic circuit diagrams. An associating unit associates the logic circuits based on at least any one of identification information, structural information, logical equivalence information, and external designated information about the logic circuits. A display format changing unit changes a display format between a side-by-side format and one-below-the-other format. A display controller performs control to display a target point in the logic circuit diagram in the same position before and after the display format is changed.

摘要翻译： 电路图显示装置显示多个逻辑电路图。 关联单元基于识别信息，结构信息，逻辑等价信息和关于逻辑电路的外部指定信息中的至少一个来关联逻辑电路。 显示格式改变单元改变并排格式和一种在另一种格式之间的显示格式。 显示控制器执行控制以在显示格式改变之前和之后在相同位置显示逻辑电路图中的目标点。

公开(公告)号：US06240541B1

公开(公告)日：2001-05-29

申请号：US09227967

申请日：1999-01-11

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有用于对要设计的电路上的每个布线路径进行延迟计算的速度分析单元和显示控制 单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US5889677A

公开(公告)日：1999-03-30

申请号：US574901

申请日：1995-12-19

申请人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

发明人： Mitsuru Yasuda ,  Hiroyuki Sugiyama ,  Noriyuki Ito ,  Ryoichi Yamashita ,  Tadashi Konno ,  Yasunori Abe ,  Naomi Bizen ,  Terunobu Maruyama ,  Yoshiyuki Kato ,  Tomoyuki Isomura ,  Hiroshi Ikeda ,  Miki Takagi

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

摘要翻译： 一种交互式的电路设计装置，其能够实现简化和高速电路设计过程，同时大大减轻设计者的负担，具有速度分析单元，用于对要设计的电路上的每个布线路径执行延迟计算，以及 显示控制单元，用于在显示单元上显示速度分析单元的延迟计算结果。 当速度分析单元进行延迟计算时，根据输入到逻辑部件的信号波形的钝度来设定和改变形成作为设计对象的电路的每个逻辑部件的延迟值。 交互式的电路设计装置可以应用于用于进行诸如LSI等的集成电路的电路设计的系统或印刷电路板。

公开(公告)号：US06618834B2

公开(公告)日：2003-09-09

申请号：US09821487

申请日：2001-03-30

申请人： Hiroji Takeyama ,  Koichi Itaya ,  Miki Takagi ,  Takehiro Yamazaki

发明人： Hiroji Takeyama ,  Koichi Itaya ,  Miki Takagi ,  Takehiro Yamazaki

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  Y10S977/839

摘要： A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.

摘要翻译： 电路设计装置包括：电路信息数据库，用于存储有关电路的信息，自动设计处理部，从电路信息数据库中读出与电路信息有关的信息，以及对每个预定处理单元设计电路;设计信息 用于存储由自动设计处理部分获得的设计信息，并且包括电路元件的特有信息，表示电路的变化历史和终端负载的历史的变化历史信息以及电路的驱动能力信息。 电路设计装置允许自动产生，再生或优化所需的电路。

公开(公告)号：US07086016B2

公开(公告)日：2006-08-01

申请号：US10453662

申请日：2003-06-04

申请人： Kazuhiro Matsuzaki ,  Hiroji Takeyama ,  Miki Takagi ,  Hiroshi Noguchi

发明人： Kazuhiro Matsuzaki ,  Hiroji Takeyama ,  Miki Takagi ,  Hiroshi Noguchi

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits includes the steps of converting into a logic circuit a logic cone that has been determined for each of the two logic circuits, the logic cone including all inputs and all logic circuits which affect one output of the combinational logic circuit, storing a logical expression converted by the converting step and a logic circuit element included in the logic cone while correlating the logical expression with the logic circuit element, and specifying the logic circuit element corresponding to a specified term in the logical expression that has been converted.

公开(公告)号：US06678871B2

公开(公告)日：2004-01-13

申请号：US10237208

申请日：2002-09-09

申请人： Hiroji Takeyama ,  Koichi Itaya ,  Miki Takagi ,  Takehiro Yamazaki

发明人： Hiroji Takeyama ,  Koichi Itaya ,  Miki Takagi ,  Takehiro Yamazaki

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  Y10S977/839

摘要： A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.

摘要翻译： 电路设计装置包括：电路信息数据库，用于存储有关电路的信息，自动设计处理部，从电路信息数据库中读出与电路信息有关的信息，以及对每个预定处理单元设计电路;设计信息 用于存储由自动设计处理部分获得的设计信息，并且包括电路元件的特有信息，表示电路的变化历史和终端负载的历史的变化历史信息以及电路的驱动能力信息。 电路设计装置允许自动产生，再生或优化所需的电路。

公开(公告)号：US08315846B2

公开(公告)日：2012-11-20

申请号：US12758133

申请日：2010-04-12

申请人： Takeo Nakamura ,  Miki Takagi ,  Junko Taira

发明人： Takeo Nakamura ,  Miki Takagi ,  Junko Taira

IPC分类号： G06G7/48

CPC分类号： G06F17/50 ,  G06F2217/10

摘要： A design data merging apparatus includes a merging determining unit that determines, for a plurality of design data of which each has product name information and has a same identifier for uniquely identifying a product, whether the product name information given to the plurality of design data are the same, and a merged data creating unit that merges the plurality of design data when it is determined by the merging determining unit that the product name information given to the plurality of design data are the same, and creates merged data obtained by merging a plurality of design data.

摘要翻译： 设计数据合并装置包括合并确定单元，对于多个设计数据，每个设计数据具有产品名称信息，并且具有用于唯一地识别产品的相同标识符，则给予多个设计数据的产品名称信息是否为 以及合并数据创建单元，当由合并确定单元确定给予多个设计数据的产品名称信息相同时，合并多个设计数据，并且创建通过合并多个设计数据获得的合并数据 的设计数据。