公开(公告)号：US08625137B2

公开(公告)日：2014-01-07

申请号：US13116153

申请日：2011-05-26

申请人： Yukio Kumazawa

发明人： Yukio Kumazawa

IPC分类号： G06F15/16

CPC分类号： G06F3/1211 ,  G06F3/1241 ,  G06F3/1259 ,  G06F3/1285

摘要： A job execution apparatus includes a partial job allocation processing section and a partial job execution instruction section. The partial job allocation processing section allocates each partial job formed by segmenting a received job to a data processing apparatus capable of executing the partial job. The partial job execution instruction section instructs the data processing apparatus to execute the partial job. The partial job allocation processing section reallocates a partial job, which execution was not completed by the data processing apparatus to which the partial job is allocated until a preset end time, to a data processing apparatus capable of executing the unfinished partial job, other than the data processing apparatus to which the unfinished partial job is allocated. The partial job execution instruction section transmits an instruction for executing the unfinished partial job to the reallocated data processing apparatus.

摘要翻译： 作业执行装置包括部分作业分配处理部和部分作业执行指示部。 部分作业分配处理部将通过将接收到的作业分割而形成的各部分作业分配给能够执行部分作业的数据处理装置。 部分作业执行指示部指示数据处理装置执行部分作业。 部分作业分配处理部将对于部分作业被分配的数据处理装置未完成的部分作业重新分配到预定的结束时间，能够执行未完成的部分作业的数据处理装置，除了 分配了未完成的部分作业的数据处理装置。 部分作业执行指令部将用于执行未完成的部分作业的指令发送到重新分配的数据处理装置。

公开(公告)号：US08041153B2

公开(公告)日：2011-10-18

申请号：US13006549

申请日：2011-01-14

申请人： Yasuhiko Kaneko ,  Junichi Kaneko ,  Satoshi Yamamoto ,  Michitaka Hariya ,  Takashi Nagao ,  Yukio Kumazawa ,  Noriaki Seki

发明人： Yasuhiko Kaneko ,  Junichi Kaneko ,  Satoshi Yamamoto ,  Michitaka Hariya ,  Takashi Nagao ,  Yukio Kumazawa ,  Noriaki Seki

IPC分类号： G06K9/60

CPC分类号： G06T1/20

摘要： A processing device has plural processing modules executing a processing; and plural connectors each having a linking section, an associating section, and a controller. The linking section is able to link with at least one other connector at an input side or an output side. The associating section associates the connector with one of the processing modules. In accordance with a linked state, the controller controls the processing module associated by the associating section.

摘要翻译： 处理装置具有执行处理的多个处理模块; 以及多个连接器，每个具有连接部分，关联部分和控制器。 连接部分能够在输入侧或输出侧与至少一个其它连接器连接。 关联部分将连接器与其中一个处理模块相关联。 根据链接状态，控制器控制由关联部分相关联的处理模块。

公开(公告)号：US20110109637A1

公开(公告)日：2011-05-12

申请号：US13006549

申请日：2011-01-14

申请人： Yasuhiko KANEKO ,  Junichi Kaneko ,  Satoshi Yamamoto ,  Michitaka Hariya ,  Takashi Nagao ,  Yukio Kumazawa ,  Noriaki Seki

发明人： Yasuhiko KANEKO ,  Junichi Kaneko ,  Satoshi Yamamoto ,  Michitaka Hariya ,  Takashi Nagao ,  Yukio Kumazawa ,  Noriaki Seki

IPC分类号： G06T1/20

CPC分类号： G06T1/20

摘要： A processing device has plural processing modules executing a processing; and plural connectors each having a linking section, an associating section, and a controller. The linking section is able to link with at least one other connector at an input side or an output side. The associating section associates the connector with one of the processing modules. In accordance with a linked state, the controller controls the processing module associated by the associating section.

摘要翻译： 处理装置具有执行处理的多个处理模块; 以及多个连接器，每个具有连接部分，关联部分和控制器。 连接部分能够在输入侧或输出侧与至少一个其它连接器连接。 关联部分将连接器与其中一个处理模块相关联。 根据链接状态，控制器控制由关联部分相关联的处理模块。

公开(公告)号：US07916974B2

公开(公告)日：2011-03-29

申请号：US11446127

申请日：2006-06-05

申请人： Yasuhiko Kaneko ,  Junichi Kaneko ,  Satoshi Yamamoto ,  Michitaka Hariya ,  Takashi Nagao ,  Yukio Kumazawa ,  Noriaki Seki

发明人： Yasuhiko Kaneko ,  Junichi Kaneko ,  Satoshi Yamamoto ,  Michitaka Hariya ,  Takashi Nagao ,  Yukio Kumazawa ,  Noriaki Seki

IPC分类号： G06K9/60

CPC分类号： G06T1/20

摘要： A processing device has plural processing modules executing a processing; and plural connectors each having a linking section, an associating section, and a controller. The linking section is able to link with at least one other connector at an input side or an output side. The associating section associates the connector with one of the processing modules. In accordance with a linked state, the controller controls the processing module associated by the associating section.

公开(公告)号：US07602392B2

公开(公告)日：2009-10-13

申请号：US11291902

申请日：2005-12-02

申请人： Takashi Nagao ,  Noriaki Seki ,  Yukio Kumazawa ,  Yasuhiko Kaneko ,  Junichi Kaneko

发明人： Takashi Nagao ,  Noriaki Seki ,  Yukio Kumazawa ,  Yasuhiko Kaneko ,  Junichi Kaneko

IPC分类号： G06F15/00 ,  G06T1/00 ,  G09G5/39 ,  G06T1/20 ,  G06F13/00

CPC分类号： G06T1/60 ,  G06T1/20

摘要： An image processing device including an image processing section and a memory managing section. The image processing section having: (A) one or more image processing modules, each having: an image processing engine and a control section; and (B) one or more buffer modules. The memory managing section (a) can execute, by a plurality of types of managing methods, memory managing processing in which, in accordance with requests from individual modules, the memory managing section reserves memories which are to be allotted to the individual modules from a memory provided at the image processing device, and allots the reserved memories to the individual modules, and, at a time of deleting the individual modules, releases the memories allotted to the individual modules, and (b) carries out the memory managing processing by a managing method which is instructed from the exterior among the plurality of types of managing methods.

摘要翻译： 一种包括图像处理部分和存储器管理部分的图像处理装置。 所述图像处理部分具有：（A）一个或多个图像处理模块，每个图像处理模块具有：图像处理引擎和控制部分; 和（B）一个或多个缓冲模块。 存储器管理部分（a）可以通过多种类型的管理方法执行存储器管理处理，其中，根据来自各个模块的请求，存储器管理部分将从各个模块分配给各个模块的存储器 存储器，并且将保留的存储器分配给各个模块，并且在删除各个模块时，释放分配给各个模块的存储器，以及（b）通过一个存储器管理处理来执行存储器管理处理 在多种类型的管理方法中从外部指示的管理方法。

公开(公告)号：US20080129740A1

公开(公告)日：2008-06-05

申请号：US11947452

申请日：2007-11-29

申请人： Kazuyuki ITAGAKI ,  Yusuke SUGIMOTO ,  Takashi IGARASHI ,  Takashi NAGAO ,  Yukio KUMAZAWA ,  Youichi ISAKA

发明人： Kazuyuki ITAGAKI ,  Yusuke SUGIMOTO ,  Takashi IGARASHI ,  Takashi NAGAO ,  Yukio KUMAZAWA ,  Youichi ISAKA

IPC分类号： G06F15/16

CPC分类号： G06F16/50

摘要： In an image processing apparatus, plural computational units execute computation relating to image processing. Plural image processing units cause the computational units to execute image processing on image information. A section number acquisition unit acquires a number of sections for sectioning the plural image processing units into groups. A sectioning unit sections the plural image processing units by causing the image processing units to belong to the respective groups based on the number of sections and the order of the image processing. A sequential storage processing unit receives requests for storage of the image information from image processing units belonging to the same group, and sequentially executes processing of the requests without performing exclusive access control. An exclusive access storage processing unit receives requests for storage of the image information from image processing units belonging to different groups, and executes processing of the requests while performing exclusive access control.

摘要翻译： 在图像处理装置中，多个计算单元执行与图像处理有关的计算。 多个图像处理单元使计算单元对图像信息执行图像处理。 段号码获取单元获取用于将多个图像处理单元分割成组的段数。 分割单元基于部分的数量和图像处理的顺序，通过使图像处理单元属于各个组来分割多个图像处理单元。 顺序存储处理单元从属于同一组的图像处理单元接收对图像信息的存储请求，并且顺序地执行请求的处理而不执行独占访问控制。 独占访问存储处理单元从属于不同组的图像处理单元接收对图像信息的存储请求，并且在执行独占访问控制的同时执行请求的处理。

公开(公告)号：US20080001953A1

公开(公告)日：2008-01-03

申请号：US11637721

申请日：2006-12-13

申请人： Takashi Nagao ,  Yukio Kumazawa ,  Youichi Isaka ,  Takashi Igarashi ,  Yusuke Sugimoto ,  Kazuyuki Itagaki ,  Junichi Kaneko

发明人： Takashi Nagao ,  Yukio Kumazawa ,  Youichi Isaka ,  Takashi Igarashi ,  Yusuke Sugimoto ,  Kazuyuki Itagaki ,  Junichi Kaneko

IPC分类号： G06F15/16

CPC分类号： G06T1/20

摘要： An image processing device including a storage section, a parallel processing controller, a sequential processing controller, and a selection section which selectively operates the two control sections. The parallel processing controller connects one or more of the image processing modules such that first buffer modules are connected at least one of preceding and following each image processing module, to formulate a first image processing section, and controls such that individual image processing modules perform image processing in parallel with one another. The first buffer modules perform exclusive access control. The sequential processing controller connects one or more of the image processing modules such that second buffer modules are connected at least one of preceding and following each image processing module, to formulate a second image processing section, and controls such that the individual image processing modules perform image processing sequentially. The second buffer modules do not perform exclusive access control.

摘要翻译： 一种图像处理装置，包括存储部分，并行处理控制器，顺序处理控制器和选择性地操作两个控制部分的选择部分。 并行处理控制器连接一个或多个图像处理模块，使得第一缓冲器模块连接到前一个和后面的每个图像处理模块中的至少一个，以形成第一图像处理部分，并且控制使得各个图像处理模块执行图像 相互并行处理。 第一个缓冲模块执行独占访问控制。 顺序处理控制器连接一个或多个图像处理模块，使得第二缓冲器模块连接到前一个和后面的每个图像处理模块中的至少一个，以形成第二图像处理部分，并且控制使得各个图像处理模块执行 图像处理顺序。 第二个缓冲模块不执行独占访问控制。

公开(公告)号：US20070006133A1

公开(公告)日：2007-01-04

申请号：US11446226

申请日：2006-06-05

申请人： Yasuhiko Kaneko ,  Junichi Kaneko ,  Satoshi Yamamoto ,  Michitaka Hariya ,  Takashi Nagao ,  Noriaki Seki ,  Yukio Kumazawa

发明人： Yasuhiko Kaneko ,  Junichi Kaneko ,  Satoshi Yamamoto ,  Michitaka Hariya ,  Takashi Nagao ,  Noriaki Seki ,  Yukio Kumazawa

IPC分类号： G06F9/44

CPC分类号： G06F8/20

摘要： A connector has a linking section, an associating section, and a controller. The linking section can link with at least one other connector at an input side or an output side. The associating section associates the connector with a processing module that executes a predetermined processing. The controller recognizes a linked state with other connectors, and, in accordance with the linked state, controls the processing module associated by the associating section.

摘要翻译： 连接器具有连接部分，关联部分和控制器。 连接部分可以在输入侧或输出侧与至少一个其它连接器连接。 关联部分将连接器与执行预定处理的处理模块相关联。 控制器识别与其他连接器的链接状态，并且根据链接状态来控制由关联部分关联的处理模块。

公开(公告)号：US20060274971A1

公开(公告)日：2006-12-07

申请号：US11291924

申请日：2005-12-02

申请人： Yukio Kumazawa ,  Takashi Nagao ,  Noriaki Seki ,  Yasuhiko Kaneko ,  Junichi Kaneko

发明人： Yukio Kumazawa ,  Takashi Nagao ,  Noriaki Seki ,  Yasuhiko Kaneko ,  Junichi Kaneko

IPC分类号： G06K9/36

CPC分类号： G06K9/00993

摘要： An image processing device has an image processing module and a buffer module. The image processing module has an image processing engine that carries out an image processing on image data. The buffer module has a buffer that stores the image data and a buffer control section that controls the amount of the image data to input into a following image processing module.

公开(公告)号：US20060274969A1

公开(公告)日：2006-12-07

申请号：US11291915

申请日：2005-12-02

申请人： Takashi Nagao ,  Noriaki Seki ,  Yukio Kumazawa ,  Youichi Isaka ,  Yasuhiko Kaneko ,  Junichi Kaneko

发明人： Takashi Nagao ,  Noriaki Seki ,  Yukio Kumazawa ,  Youichi Isaka ,  Yasuhiko Kaneko ,  Junichi Kaneko

IPC分类号： G06K9/36

CPC分类号： G06T1/20

摘要： An image processing device including an image processing section having one or more image processing modules and buffer modules having a buffer is provided. The buffer module, recognizes a number of image processing modules which are connected at the following stage of its own module; stores, for each of the following image processing modules, a head position of un-read image data among image data which is stored in the buffer; and each time image data is requested from an following image processing module, causes the image processing module to read, in a read data amount which is set in advance for its own module at each of the individual following image processing modules or which is designated each time of the request, image data which is stored in the buffer, from the head position corresponding to the image processing module.