公开(公告)号：US06867632B2

公开(公告)日：2005-03-15

申请号：US10648475

申请日：2003-08-27

申请人： Yusuke Nitta ,  Toshihiro Hattori

发明人： Yusuke Nitta ,  Toshihiro Hattori

IPC分类号： H01L21/822 ,  G06F1/10 ,  H01L27/04 ,  H03L7/00 ,  H03K19/096

CPC分类号： G06F1/10 ,  H03L7/00

摘要： A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

摘要翻译： 用于最小化时钟布线的半导体集成电路器件缩短了布线延迟。 在从时钟发生器到触发器的时钟布线路径上提供多级时钟驱动器。 连接上级时钟驱动器的时钟线以树结构的形式被长度均衡化，并且连接下级时钟驱动器的时钟线尽可能短。

公开(公告)号：US06636095B2

公开(公告)日：2003-10-21

申请号：US10238716

申请日：2002-09-11

申请人： Yusuke Nitta ,  Toshihiro Hattori

发明人： Yusuke Nitta ,  Toshihiro Hattori

IPC分类号： H03K19096

CPC分类号： G06F1/10 ,  H03L7/00

摘要： A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

公开(公告)号：US06246277B1

公开(公告)日：2001-06-12

申请号：US09209006

申请日：1998-12-11

申请人： Yusuke Nitta ,  Toshihiro Hattori

发明人： Yusuke Nitta ,  Toshihiro Hattori

IPC分类号： H03K19096

CPC分类号： G06F1/10 ,  H03L7/00

摘要： A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

摘要翻译： 用于最小化时钟布线的半导体集成电路器件缩短了布线延迟。 在从时钟发生器到触发器的时钟布线路径上提供多级时钟驱动器。 连接上级时钟驱动器的时钟线以树结构的形式被长度均衡化，并且连接下级时钟驱动器的时钟线尽可能短。

公开(公告)号：US06462599B2

公开(公告)日：2002-10-08

申请号：US09861600

申请日：2001-05-22

申请人： Yusuke Nitta ,  Toshihiro Hattori

发明人： Yusuke Nitta ,  Toshihiro Hattori

IPC分类号： H03K19096

CPC分类号： G06F1/10 ,  H03L7/00

摘要： A semiconductor integrated circuit device for minimizing clock skew over clock wiring shortened for reduced wiring delays. A plurality of stages of clock drivers are provided on clock wiring paths ranging from a clock generator to flip-flops. Clock lines connecting upper stage clock drivers are equalized in length in the form of a tree structure, and clock lines connecting lower stage clock drivers are made as short as possible.

摘要翻译： 用于最小化时钟布线的半导体集成电路器件缩短了布线延迟。 在从时钟发生器到触发器的时钟布线路径上提供多级时钟驱动器。 连接上级时钟驱动器的时钟线以树结构的形式被长度均衡化，并且连接下级时钟驱动器的时钟线尽可能短。