公开(公告)号：US11189688B2

公开(公告)日：2021-11-30

申请号：US17285415

申请日：2019-09-13

Applicant: ABB Power Grids Switzerland AG

Inventor： Luca De-Michielis ,  Munaf Rahimo ,  Chiara Corvasce

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/739

Abstract: An insulated gate power semiconductor device (1a), comprises in an order from a first main side (20) towards a second main side (27) opposite to the first main side (20) a first conductivity type source layer (3), a second conductivity type base layer (4), a first conductivity type enhancement layer (6) and a first conductivity type drift layer (5). The insulated gate power semiconductor device (1a) further comprises two neighbouring trench gate electrodes (7) to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (7). At least a portion of a second conductivity type protection layer (8a) is arranged in an area between the two neighbouring trench gate electrodes (7), wherein the protection layer (8a) is separated from the gate insulating layer (72) by a first conductivity type channel layer (60a; 60b) extending along the gate insulating layer (72).

公开(公告)号：US20210320170A1

公开(公告)日：2021-10-14

申请号：US17285415

申请日：2019-09-13

Applicant: ABB Power Grids Switzerland AG

Inventor： Luca De-Michielis ,  Munaf Rahimo ,  Chiara Corvasce

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265

Abstract: An insulated gate power semiconductor device (1a), comprises in an order from a first main side (20) towards a second main side (27) opposite to the first main side (20) a first conductivity type source layer (3), a second conductivity type base layer (4), a first conductivity type enhancement layer (6) and a first conductivity type drift layer (5). The insulated gate power semiconductor device (1a) further comprises two neighbouring trench gate electrodes (7) to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (7). At least a portion of a second conductivity type protection layer (8a) is arranged in an area between the two neighbouring trench gate electrodes (7), wherein the protection layer (8a) is separated from the gate insulating layer (72) by a first conductivity type channel layer (60a; 60b) extending along the gate insulating layer (72).

公开(公告)号：US11075285B2

公开(公告)日：2021-07-27

申请号：US16157435

申请日：2018-10-11

Applicant: ABB Power Grids Switzerland AG

Inventor： Luca De-Michielis ,  Chiara Corvasce

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L29/08 ,  H01L21/266

Abstract: An insulated gate power semiconductor device includes an (n-) doped drift layer between an emitter side and a collector side. A p doped protection pillow covers a trench bottom of a trench gate electrode. An n doped enhancement layer having a maximum enhancement layer doping concentration in an enhancement layer depth separates the base layer from the drift layer. An n doped plasma enhancement layer having a maximum plasma enhancement layer doping concentration covers an edge region between the protection pillow and the trench gate electrode. The N doping concentration decreases from the maximum enhancement layer doping concentration towards the plasma enhancement layer and the N doping concentration decreases from the maximum plasma enhancement layer doping concentration towards the enhancement layer such that the N doping concentration has a local doping concentration minimum between the enhancement layer and the plasma enhancement layer.