公开(公告)号：US20180309308A1

公开(公告)日：2018-10-25

申请号：US15956290

申请日：2018-04-18

申请人： ABLIC Inc.

发明人： Hiroshi SAITO ,  Akihiko SUZUKI ,  Takahiro KURATOMI

IPC分类号： H02J7/00

CPC分类号： H02J7/0031 ,  G01R31/362 ,  H02J7/0011 ,  H02J7/0036 ,  H02J7/0086 ,  H02J2007/0037 ,  H02J2007/0039 ,  H02J2007/004

摘要： A charge/discharge control circuit includes a control circuit which outputs a control signal to a charge control terminal and a discharge control terminal respectively, a charge/discharge monitoring circuit which monitors charge/discharge of a secondary battery, a charger detection circuit connected to a charger detection terminal and configured to detect a charger connection, and a load open detection circuit connected to the charger detection terminal and configured to detect a state of a load. In response to reception of a signal to instruct turning on of a charge control FET from the charger detection circuit, the control circuit turns on the charge control FET even when the control circuit turned off the charge control FET in response to the signal to instruct turning off of the charge control FET from the charge/discharge monitoring circuit.

公开(公告)号：US20240333005A1

公开(公告)日：2024-10-03

申请号：US18604517

申请日：2024-03-14

申请人： ABLIC Inc.

发明人： Shinya FUKUCHI ,  Hiroshi SAITO ,  Keiichi MURAKAWA

IPC分类号： H02J7/00 ,  G01R31/396 ,  H01M10/46 ,  H01M50/204 ,  H01M50/51

CPC分类号： H02J7/0047 ,  G01R31/396 ,  H01M10/46 ,  H01M50/204 ,  H01M50/51 ,  H02J7/0013 ,  H02J7/00712

摘要： A cell number determination device, a charge and discharge control device, and a battery device with small circuit scale are provided. The cell number determination device includes: multiple differential amplifiers provided corresponding to multiple cells in a battery pack, of which the cell number is changeable, equipped with multiple cells connected in series; and multiple output circuits provided corresponding to the differential amplifiers. An input differential pair of the differential amplifiers includes a heteropolar gate NMOS transistor and an NMOS transistor.

公开(公告)号：US20180262035A1

公开(公告)日：2018-09-13

申请号：US15894441

申请日：2018-02-12

申请人： ABLIC Inc.

发明人： Hiroshi SAITO ,  Fumihiko MAETANI ,  Akihiko SUZUKI ,  Takahiro KURATOMI

IPC分类号： H02J7/00

CPC分类号： H02J7/0068 ,  H02J7/0029 ,  H02J7/0031 ,  H02J7/0047 ,  H02J7/0072 ,  H02J2007/004 ,  H02J2007/005

摘要： A charge/discharge control circuit includes: a first power supply terminal connected to a first electrode of a secondary battery; a second power supply terminal connected to a second electrode of the secondary battery; a control circuit configured to control charge/discharge of the secondary battery; and a power-down release pulse generation circuit connected to the power-down release terminal, the power-down release pulse generation circuit being configured to supply, in a power-down state of the charge/discharge control circuit, a power-down release pulse at least to the control circuit in response to an input of a power-down release signal to the power-down release terminal to release the power-down state.

公开(公告)号：US20180269705A1

公开(公告)日：2018-09-20

申请号：US15918362

申请日：2018-03-12

申请人： ABLIC Inc.

发明人： Hiroshi SAITO ,  Kazuaki SANO ,  Takahiro KASHIUCHI ,  Akihiko SUZUKI ,  Takahiro KURATOMI

IPC分类号： H02J7/00

摘要： A charge and discharge control circuit operates between a first and a second power supply voltage of the secondary battery, and is used in a cascade-connection to the second charge and discharge control circuit having the same configuration, and includes an output circuit and an output terminal for discharge control, an input circuit and an input terminal for discharge control, and a control circuit. The input circuit includes a first MOS transistor having a source terminal connected to the input terminal and a gate terminal for receiving the first power supply voltage, a second MOS transistor having a drain terminal and a gate terminal connected to a drain terminal of the first MOS transistor and a source terminal for receiving the second power supply voltage, and a third MOS transistor current-mirror-connected to the second MOS transistor and having a drain terminal for supplying a discharge control input signal.

公开(公告)号：US20230006459A1

公开(公告)日：2023-01-05

申请号：US17844060

申请日：2022-06-20

申请人： ABLIC Inc.

发明人： Fumihiko MAETANI ,  Hiroshi SAITO

IPC分类号： H02J7/00 ,  G01R31/3835 ,  G01R31/396 ,  H01M50/204 ,  H01M10/44 ,  H01M50/51 ,  H01M50/583 ,  H01M50/296 ,  H01M10/48 ,  H01M10/46

摘要： The charge control circuit includes a cell connection detection circuit monitoring a voltage between input ports to which terminals of a cell pack are connected, an overvoltage detection circuit monitoring an overvoltage of the secondary cells, a first latch circuit receiving a signal output by the cell connection detection circuit, a second latch circuit receiving a signal output by the overvoltage detection circuit, a reset circuit outputting a signal to the first latch circuit and the second latch circuit when the charge control circuit is activated, and a control circuit receiving a signal output from the second latch circuit and outputting a signal for protecting the cell pack from the overvoltage. The control circuit does not output a signal for blowing the fuse until the first latch circuit receives a detection signal of the cell connection detection circuit.

公开(公告)号：US20180301921A1

公开(公告)日：2018-10-18

申请号：US15951939

申请日：2018-04-12

申请人： ABLIC Inc.

发明人： Hiroshi SAITO ,  Akihiko SUZUKI ,  Takahiro KURATOMI

IPC分类号： H02J7/00

CPC分类号： H02J7/0068 ,  H02J7/0031 ,  H02J7/0047 ,  H02J7/0081 ,  H02J7/0086

摘要： A charge/discharge control circuit includes a first power supply terminal connected to a first electrode of a secondary battery, and a discharge control output circuit which outputs a discharge control signal to a gate of a discharge control FET which controls discharging of the secondary battery. The discharge control output circuit includes a clamp voltage output circuit which outputs a clamp voltage lower than a voltage of the first power supply terminal to a discharge control terminal to turn on the discharge control FET when the voltage of the first power supply terminal is higher than a prescribed voltage, and a power supply voltage output circuit which outputs the voltage of the first power supply terminal to the discharge control terminal to turn on the discharge control FET when the voltage of the first power supply terminal is equal to or less than the prescribed voltage.