公开(公告)号：US20140244932A1

公开(公告)日：2014-08-28

申请号：US13779573

申请日：2013-02-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Akarsh D. Hebbar ,  James D. Dundas ,  Robert B. Cohen

IPC: G06F12/08

CPC classification number: G06F12/0875

Abstract: The present invention provides a method and apparatus for caching pre-decode information. Some embodiments of the apparatus include a first pre-decode array configured to store pre-decode information for an instruction cache line that is resident in a first cache in response to the instruction cache line being evicted from one or more second cache(s). Some embodiments of the apparatus also include a second array configured to store a plurality of bits associated with the first cache. Subsets of the bits are configured to store pointers to the pre-decode information associated with the instruction cache line.

Abstract translation: 本发明提供了一种用于缓存预解码信息的方法和装置。 该装置的一些实施例包括第一预解码阵列，其被配置为存储响应于从一个或多个第二高速缓存逐出的指令高速缓存行驻留在第一高速缓存中的指令高速缓存线的预解码信息。 该装置的一些实施例还包括被配置为存储与第一高速缓存相关联的多个位的第二阵列。 位的子集被配置为存储与指令高速缓存行相关联的预解码信息的指针。