公开(公告)号：US20140164748A1

公开(公告)日：2014-06-12

申请号：US13711403

申请日：2012-12-11

Applicant: Advanced Micro Devices, Inc.

Inventor： James D. Dundas

IPC: G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/3806 ,  G06F12/0862

Abstract: The present application describes a method and apparatus for prefetching instructions based on predicted branch target addresses. Some embodiments of the method include providing a second cache line to a second cache when a target address for a branch instruction in a first cache line of a first cache is included in the second cache line of the first cache and when the second cache line is not resident in the second cache.

Abstract translation: 本申请描述了一种基于预测的分支目标地址来预取指令的方法和装置。 当第一高速缓存的第一高速缓存行中的分支指令的目标地址被包括在第一高速缓存的第二高速缓存行中时，并且当第二高速缓存行是第二高速缓存行时，该方法的一些实施例包括向第二高速缓存提供第二高速缓存行 不驻留在第二个缓存中。

公开(公告)号：US20140244932A1

公开(公告)日：2014-08-28

申请号：US13779573

申请日：2013-02-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Akarsh D. Hebbar ,  James D. Dundas ,  Robert B. Cohen

IPC: G06F12/08

CPC classification number: G06F12/0875

Abstract: The present invention provides a method and apparatus for caching pre-decode information. Some embodiments of the apparatus include a first pre-decode array configured to store pre-decode information for an instruction cache line that is resident in a first cache in response to the instruction cache line being evicted from one or more second cache(s). Some embodiments of the apparatus also include a second array configured to store a plurality of bits associated with the first cache. Subsets of the bits are configured to store pointers to the pre-decode information associated with the instruction cache line.

Abstract translation: 本发明提供了一种用于缓存预解码信息的方法和装置。 该装置的一些实施例包括第一预解码阵列，其被配置为存储响应于从一个或多个第二高速缓存逐出的指令高速缓存行驻留在第一高速缓存中的指令高速缓存线的预解码信息。 该装置的一些实施例还包括被配置为存储与第一高速缓存相关联的多个位的第二阵列。 位的子集被配置为存储与指令高速缓存行相关联的预解码信息的指针。

公开(公告)号：US20140115257A1

公开(公告)日：2014-04-24

申请号：US13657254

申请日：2012-10-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James D. Dundas

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/6024

Abstract: A processor stores branch information at a “sparse” cache and a “dense” cache. The sparse cache stores the target addresses for up to a specified number of branch instructions in a given cache entry associated with a cache line address, while branch information for additional branch instructions at the cache entry is stored at the dense cache. Branch information at the dense cache persists after eviction of the corresponding cache line until it is replaced by branch information for a different cache entry. Accordingly, in response to the instructions for a given cache line address being requested for retrieval from memory, a prefetcher determines whether the dense cache stores branch information for the cache line address. If so, the prefetcher prefetches the instructions identified by the target addresses of the branch information in the dense cache concurrently with transferring the instructions associated with the cache line address.

Abstract translation: 处理器将分支信息存储在“稀疏”高速缓存和“密集”高速缓存中。 稀疏高速缓存存储与高速缓存行地址相关联的给定高速缓存条目中指定数目的分支指令的目标地址，而高速缓存条目处的附加分支指令的分支信息存储在密集高速缓存中。 密集缓存中的分支信息在驱逐相应的高速缓存行之后仍然存在，直到被替换为不同缓存条目的分支信息为止。 因此，响应于针对从存储器检索的给定高速缓存行地址的指令，预取器确定密集高速缓存是否存储用于高速缓存行地址的分支信息。 如果是这样，预取器在传送与高速缓存线地址相关联的指令的同时，预先在密集高速缓存中预取由分支信息的目标地址标识的指令。