PSEUDO-RANDOM LOGICAL TO PHYSICAL CORE ASSIGNMENT AT BOOT FOR AGE AVERAGING

    公开(公告)号:US20190188001A1

    公开(公告)日:2019-06-20

    申请号:US15846781

    申请日:2017-12-19

    CPC classification number: G06F9/4408 G06F9/4403

    Abstract: A computing device includes a processor having a plurality of cores, a core translation component, and a core assignment component. The core translation component provides a set of registers, one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transferred to a respective core based on the core indices.

    ONBOARD MONITORING OF VOLTAGE LEVELS AND DROOP EVENTS

    公开(公告)号:US20190265767A1

    公开(公告)日:2019-08-29

    申请号:US15907744

    申请日:2018-02-28

    Abstract: A processor includes a plurality of voltage droop detectors positioned at multiple points of a processor. The detectors monitor voltage levels and alert the processor if a droop event has been detected in real time. Multiple droops can be detected simultaneously, with each detected droop event generating an alert that is sent to a processor module, such as a clock control module, to act based on the detected droop. Each detector employs a ring oscillator that generates a periodic signal and a corresponding count based on that signal, where the frequency of the signal varies based on a voltage at the corresponding point being monitored.

    PREDICTING PROCESSOR POWER DISTURBANCES BY MONITORING PERFORMANCE CHARACTERISTICS

    公开(公告)号:US20190310698A1

    公开(公告)日:2019-10-10

    申请号:US15949662

    申请日:2018-04-10

    Inventor: Amitabh MEHRA

    Abstract: A monitoring system predicts voltage droops at a processor by monitoring one or more performance characteristics of the processor, selecting a response policy based on the prediction, and adjusting a parameter of the processor. Multiple predictions of voltage droop conditions at different locations of the processor are made simultaneously, with the processor generating one or more responses and resulting in adjusting one or more parameters of the processor. By predicting voltage droop conditions before they occur, the deleterious effects of such droop conditions can be minimized or avoided.

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