公开(公告)号：US20220100663A1

公开(公告)日：2022-03-31

申请号：US17116950

申请日：2020-12-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. COHEN ,  Tzu-Wei LIN ,  Anthony J. BYBELL ,  Sudherssen KALAISELVAN ,  James MOSSMAN

IPC: G06F12/0855

Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.

公开(公告)号：US20220100519A1

公开(公告)日：2022-03-31

申请号：US17032494

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. COHEN ,  Tzu-Wei LIN ,  Anthony J. BYBELL ,  Bill Kai Chiu KWAN ,  Frank C. GALLOWAY

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor employs a plurality of fetch and decode pipelines by dividing an instruction stream into instruction blocks with identified boundaries. The processor includes a branch predictor that generates branch predictions. Each branch prediction corresponds to a branch instruction and includes a prediction that the corresponding branch is to be taken or not taken. In addition, each branch prediction identifies both an end of the current branch prediction window and the start of another branch prediction window. Using these known boundaries, the processor provides different sequential fetch streams to different ones of the plurality of fetch and decode states, which concurrently process the instructions of the different fetch streams, thereby improving overall instruction throughput at the processor.