公开(公告)号：US20220100663A1

公开(公告)日：2022-03-31

申请号：US17116950

申请日：2020-12-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Robert B. COHEN ,  Tzu-Wei LIN ,  Anthony J. BYBELL ,  Sudherssen KALAISELVAN ,  James MOSSMAN

IPC: G06F12/0855

Abstract: A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.