公开(公告)号：US20210191722A1

公开(公告)日：2021-06-24

申请号：US17169053

申请日：2021-02-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arunachalam ANNAMALAI ,  Marius EVERS ,  Aparna THYAGARAJAN ,  Anthony JARVIS

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3296

Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

公开(公告)号：US20200089498A1

公开(公告)日：2020-03-19

申请号：US16134440

申请日：2018-09-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arunachalam ANNAMALAI ,  Marius EVERS ,  Aparna THYAGARAJAN

IPC: G06F9/30 ,  G06F1/32 ,  G06F9/38

Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

公开(公告)号：US20200034151A1

公开(公告)日：2020-01-30

申请号：US16043293

申请日：2018-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Aparna THYAGARAJAN ,  Marius EVERS ,  Arunachalam ANNAMALAI

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor includes a branch target buffer (BTB) having a plurality of entries whereby each entry corresponds to an associated instruction pointer value that is predicted to be a branch instruction. Each BTB entry stores a predicted branch target address for the branch instruction, and further stores information indicating whether the next branch in the block of instructions associated with the predicted branch target address is predicted to be a return instruction. In response to the BTB indicating that the next branch is predicted to be a return instruction, the processor initiates an access to a return stack that stores the return address for the predicted return instruction. By initiating access to the return stack responsive to the return prediction stored at the BTB, the processor reduces the delay in identifying the return address, thereby improving processing efficiency.