公开(公告)号：US20190189196A1

公开(公告)日：2019-06-20

申请号：US15841649

申请日：2017-12-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew ROBISON ,  Michael K. CIRAULA ,  Eric BUSTA ,  Carson Donahue HENRION

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.