公开(公告)号：US20190189196A1

公开(公告)日：2019-06-20

申请号：US15841649

申请日：2017-12-14

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Andrew ROBISON ,  Michael K. CIRAULA ,  Eric BUSTA ,  Carson Donahue HENRION

IPC分类号： G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C11/418

摘要： A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.

公开(公告)号：US20190188064A1

公开(公告)日：2019-06-20

申请号：US15849071

申请日：2017-12-20

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Michael K. CIRAULA

IPC分类号： G06F11/07 ,  G11C29/10 ,  G06F11/34 ,  G06F9/30

CPC分类号： G06F11/2215 ,  G06F9/30029 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0793 ,  G06F11/1068 ,  G06F11/3409 ,  G11C29/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/56004 ,  G11C29/72 ,  G11C2029/0401 ,  G11C2029/1202 ,  G11C2029/4402 ,  H03M13/015

摘要： A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.

公开(公告)号：US20190129651A1

公开(公告)日：2019-05-02

申请号：US15794457

申请日：2017-10-26

申请人： ADVANCED MICRO DEVICES, INC.

发明人： John WUU ,  Michael K. CIRAULA ,  Russell SCHREIBER ,  Samuel NAFFZIGER

IPC分类号： G06F3/06 ,  G06F12/1009

摘要： A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.