公开(公告)号：US20210109861A1

公开(公告)日：2021-04-15

申请号：US16600897

申请日：2019-10-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jieming YIN ,  Subhash SETHUMURUGAN ,  Yasuko ECKERT

IPC: G06F12/0891 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0897 ,  G06F12/126

Abstract: A cache of a processor includes a cache controller to implement a cache management policy for the insertion and replacement of cache lines of the cache. The cache management policy assigns replacement priority levels to each cache line of at least a subset of cache lines in a region of the cache based on a comparison of a number of accesses to a cache set having a way that stores a cache line since the cache line was last accessed to a reuse distance determined for the region of the cache, wherein the reuse distance represents an average number of accesses to a given cache set of the region between accesses to any given cache line of the cache set.