公开(公告)号：US20200065108A1

公开(公告)日：2020-02-27

申请号：US16106515

申请日：2018-08-21

Applicant: Advanced Micro Devices, Inc.

Inventor： ANDREJ KOCEV ,  JAY FLEISCHMAN ,  KAI TROESTER ,  JOHNNY C. CHU ,  TIM J. WILKENS ,  NEIL MARKETKAR ,  MICHAEL W. LONG

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.

公开(公告)号：US20230315454A1

公开(公告)日：2023-10-05

申请号：US17708216

申请日：2022-03-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： KAI TROESTER

IPC: G06F9/30

CPC classification number: G06F9/30076 ,  G06F9/3004

Abstract: A method of fusing no-op (NOP) instructions includes receiving a no-op (NOP) instruction and generating, based on the NOP instruction and at least one other instruction, a fused NOP instruction.