公开(公告)号：US20210343066A1

公开(公告)日：2021-11-04

申请号：US17230140

申请日：2021-04-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. KAZAKOV ,  Mark FOWLER

IPC: G06T15/04 ,  G06T15/00

Abstract: A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps that indicate texels that are resident in the PRT resource. The processor translates the normalized coordinates to texel coordinates in the one or more residency maps based on the offset and accesses, in response to the request, the one or more residency maps based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.

公开(公告)号：US20200310684A1

公开(公告)日：2020-10-01

申请号：US16370035

申请日：2019-03-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark FOWLER

IPC: G06F3/06 ,  G06F12/10

Abstract: A processing unit is configured to access a first memory that supports atomic operations and a second memory via an interface. The second memory or the interface does not support atomicity of the atomic operations. A trap handler is configured to trap atomic operations and enforce atomicity of the trapped atomic operations. The processing unit selectively provides atomic operations to the trap handler in response to detecting that memory access requests in the atomic operations are directed to the second memory via the interface. In some cases, the processing unit detects a frequency of traps that result from atomic operations that include memory access requests to a page stored in the second memory. The processing unit transfers the page from the second memory to the first memory in response to the trap frequency exceeding a threshold.

公开(公告)号：US20200250877A1

公开(公告)日：2020-08-06

申请号：US16723232

申请日：2019-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. KAZAKOV ,  Mark FOWLER

IPC: G06T15/04 ,  G06T15/00

Abstract: A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps that indicate texels that are resident in the PRT resource. The processor translates the normalized coordinates to texel coordinates in the one or more residency maps based on the offset and accesses, in response to the request, the one or more residency maps based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.