公开(公告)号：US20150205721A1

公开(公告)日：2015-07-23

申请号：US14160552

申请日：2014-01-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Stephan Diestelhorst ,  Martin T. Pohlack ,  Michael P. Hohmuth

IPC: G06F12/08 ,  G06F9/46

CPC classification number: G06F12/0811

Abstract: The described embodiments include a computing device that handles cache blocks during a transaction. In the described embodiments, after an entity has written to a cache block in a cache during the transaction, the computing device responds to a read request for the cache block from another entity with a copy of the cache block in a pre-transactional state. In these embodiments, the entity executing the transaction continues the transaction after the computing device responds to the read request from the other entity.

Abstract translation: 所描述的实施例包括在事务期间处理高速缓存块的计算设备。 在所描述的实施例中，在事务中实体已经写入高速缓存中的高速缓存块之后，计算设备响应来自另一实体的高速缓存块的读取请求，其中高速缓存块的副本处于事务前状态。 在这些实施例中，执行事务的实体在计算设备响应来自另一实体的读取请求之后继续进行事务。

公开(公告)号：US10956163B2

公开(公告)日：2021-03-23

申请号：US15845641

申请日：2017-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jaewoong Chung ,  David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst ,  Martin Pohlack ,  Luke Yen

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46

Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.