公开(公告)号：US20230096002A1

公开(公告)日：2023-03-30

申请号：US17890520

申请日：2022-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar SAJJA ,  Sreekanth GODEY ,  Anirudh R. ACHARYA

IPC: G06F1/08 ,  G06F9/50 ,  G06F11/34 ,  G06F1/12

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

公开(公告)号：US20240345617A1

公开(公告)日：2024-10-17

申请号：US18603883

申请日：2024-03-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar SAJJA ,  Sreekanth GODEY ,  Anirudh R. ACHARYA

IPC: G06F1/08 ,  G06F1/12 ,  G06F9/50 ,  G06F11/34

CPC classification number: G06F1/08 ,  G06F1/12 ,  G06F9/505 ,  G06F11/3409

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

公开(公告)号：US20210278873A1

公开(公告)日：2021-09-09

申请号：US17032701

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar SAJJA ,  Sreekanth GODEY ,  Anirudh R. ACHARYA

IPC: G06F1/08 ,  G06F1/12 ,  G06F9/50 ,  G06F11/34

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.