PREDICTIVE PERIODIC SYNCHRONIZATION USING PHASE-LOCKED LOOP DIGITAL RATIO UPDATES
    1.
    发明申请
    PREDICTIVE PERIODIC SYNCHRONIZATION USING PHASE-LOCKED LOOP DIGITAL RATIO UPDATES 有权
    使用相位锁定数字比例更新的预测周期同步

    公开(公告)号:US20150117582A1

    公开(公告)日:2015-04-30

    申请号:US14064045

    申请日:2013-10-25

    CPC classification number: H04L7/0331 G06F1/12 H03J1/005 H03L7/00 H04L7/0012

    Abstract: Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.

    Abstract translation: 描述了实现方案和系统,使得能够将来自时钟控制器的更新直接发送到预测同步器以管理发射和接收时钟域之间的频率的即时变化,包括从锁相环电路接收接收和发送参考频率 从耦合到锁相环电路的控制器接收和发送恒定码,获得延时因子以适应发射和接收时钟域之间的相位检测,并使用时间延迟因子计算新的检测间隔和频率信息, 参考频率和常数码。

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