公开(公告)号：US20190146567A1

公开(公告)日：2019-05-16

申请号：US15809419

申请日：2017-11-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Stephen Victor KOSONOCKY ,  Larry D. HEWITT ,  Erik SWANSON

IPC: G06F1/32

Abstract: A processor is throttled based on accumulated combined current measurements from a plurality of processor cores. The processor monitors activity current levels at each processor core, either directly or indirectly by monitoring specified events at the processor cores. The processor combines (e.g., averages) the activity current levels over a specified duration to determine a combined activity current value (CCV), and compares the CCV value to a threshold, wherein the threshold is based on the maximum current limit of the processor. In response to the CCV exceeding the threshold, the processor throttles one or more of the processor cores, thereby reducing the activity current level at the throttled processor cores and ensuring that the processor operates within its specified current limits.

公开(公告)号：US20190317546A1

公开(公告)日：2019-10-17

申请号：US15954051

申请日：2018-04-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Richard Martin BORN ,  Stephen Victor KOSONOCKY ,  Miguel RODRIGUEZ

IPC: G06F1/08 ,  H03K5/00 ,  G06F1/28 ,  G06F1/30

Abstract: A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.