公开(公告)号：US11544065B2

公开(公告)日：2023-01-03

申请号：US16585817

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arun A. Nair ,  Todd Baumgartner ,  Michael Estlick ,  Erik Swanson

IPC: G06F9/30

Abstract: A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.

公开(公告)号：US20230034072A1

公开(公告)日：2023-02-02

申请号：US17389838

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Estlick ,  Erik Swanson ,  Eric Dixon ,  Todd Baumgartner

IPC: G06F9/38 ,  G06F9/30

Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.

公开(公告)号：US11960897B2

公开(公告)日：2024-04-16

申请号：US17389838

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Estlick ,  Erik Swanson ,  Eric Dixon ,  Todd Baumgartner

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3869 ,  G06F9/30123

Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.