公开(公告)号：US20210398242A1

公开(公告)日：2021-12-23

申请号：US17128388

申请日：2020-12-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Noor Mohammed Saleem BIJAPUR ,  Ashish KHANDELWAL ,  Laurent LEFEBVRE ,  Anirudh R. ACHARYA

IPC: G06T1/20 ,  G06T1/60 ,  G06F12/0806 ,  G06F12/0888

Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.