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公开(公告)号:US20240039694A1
公开(公告)日:2024-02-01
申请号:US18254132
申请日:2021-11-24
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor: Hong YANG , Dee Meng KANG , Ahmad Qaisar Ahmad AL BADAWI , Khin Mi Mi AUNG
CPC classification number: H04L9/008 , G06F9/3875 , G06F7/724
Abstract: There is provided a device for processing homomorphically encrypted data. The device includes: inter-line butterfly array blocks, each inter-line butterfly array block including inter-line modulus butterfly units, each inter-line modulus butterfly unit being configured to perform a modulus butterfly operation based on a computation pair of data points received corresponding to a pair of input data points at a same row of a matrix of input data points; intra-line butterfly array blocks, each intra-line butterfly array block including intra-line modulus butterfly units, each intra-line modulus butterfly unit being configured to perform a modulus butterfly operation based on a computation pair of data points received corresponding to a pair of input data points at a same column of the matrix of input data points; and a clock counter communicatively coupled to each inter-line butterfly array block and each intra-line butterfly array block, and configured to output a counter signal for controlling each inter-line butterfly array block and each intra-line butterfly array block to operate with single cycle initiation interval. The matrix of input data points includes columns of input data points, whereby parallel input data points derived from the homomorphically encrypted data are arranged into the columns of input data points. Furthermore, the inter-line butterfly array blocks and the intra-line butterfly array blocks are arranged in series to form a pipeline for processing the matrix of input data points.
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公开(公告)号:US20170270044A1
公开(公告)日:2017-09-21
申请号:US15506565
申请日:2015-10-02
Applicant: Agency for Science, Technology and Research
Inventor: Hong YANG , Khai Leong YONG , Dee Meng KANG
IPC: G06F12/0804 , G06F3/06
CPC classification number: G06F12/0804 , G06F3/0605 , G06F3/0607 , G06F3/0613 , G06F3/0617 , G06F3/0629 , G06F3/0647 , G06F3/0685 , G06F3/0689 , G06F2212/1032
Abstract: An active storage unit and an active storage array are provided. The active storage unit includes an active control board having a processor, at least one internal memory module communicatively coupled to the processor, and a reconfigurable logic circuit communicatively coupled to the processor for programming the active storage unit. The active storage unit also includes a plurality of storage devices communicatively coupled to the active control board.
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