-
1.
公开(公告)号:US20230243030A1
公开(公告)日:2023-08-03
申请号:US18012412
申请日:2021-06-28
Applicant: Agency for Science, Technology and Research
Inventor: Henry Medina Silva , Dongzhi Chi , Shi Wun Tong , Jianwei Chai , Shijie Wang
IPC: C23C16/02 , C23C14/18 , C23C14/08 , C23C16/448 , C23C16/30 , C23C16/455 , C23C16/46 , C23C14/58 , C23C28/00 , H01L21/02
CPC classification number: C23C16/0281 , C23C14/083 , C23C14/185 , C23C14/5866 , C23C16/46 , C23C16/305 , C23C16/4482 , C23C16/45523 , C23C28/322 , C23C28/3455 , H01L21/0242 , H01L21/02568 , H01L21/02614
Abstract: A method for forming a transition metal dichalcogenide monolayer, which includes depositing a transition metal, a transition metal oxide, or a mixture thereof, on a substrate, introducing a chalcogen precursor to the transition metal, the transition metal oxide, or the mixture thereof, in the presence of an etching gas and a carrier gas at a first temperature, to form a transition metal dichalcogenide on the substrate from the transition metal, the transition metal oxide, or the mixture thereof, and subliming the transition metal dichalcogenide on the substrate in the presence of a pulsating supply of a vapor of the chalcogen precursor to form the transition metal dichalcogenide monolayer at a second temperature, wherein the vapor of the chalcogen precursor comprises a chalcogen vapor.
-
公开(公告)号:US12245531B2
公开(公告)日:2025-03-04
申请号:US17636833
申请日:2020-09-18
Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
Inventor: Henry Medina Silva , Dongzhi Chi , Jianwei Chai , Ming Yang , Shijie Wang , Shi Wun Tong , Carlos Manzano
Abstract: Herein provided is a multilayered structure including one or more nanocrystalline layers each comprising a transition metal dichalcogenide, one or more substantially amorphous electrically insulating layers each comprising a transition metal oxide, wherein the transition metal oxide comprises a transition metal which is identical to the transition metal of the transition metal dichalcogenide, wherein the one or more nanocrystalline layers and the one or more substantially amorphous electrically insulating layers are formed in an alternating manner, and wherein each of the one or more nanocrystalline layers is formed adjacent to the substantially amorphous insulating layer. A resistive memory device comprising the multilayered structure and a process of fabricating the multilayered structure are also disclosed herein.
-