-
公开(公告)号：US20240069954A1
公开(公告)日：2024-02-29
申请号：US18322954
申请日：2023-05-24
发明人： TIANCHAN GUAN , DIMIN NIU , YIJIN GUAN , HONGZHONG ZHENG
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F2009/4557 , G06F2009/45583
摘要： The present application discloses a computing system and a memory sharing method for a computing system. The computing system includes a first host, a second host, a first memory extension device and a second memory extension device. The first memory extension device is coupled to the first host. The second memory extension device is coupled to the second host and the first memory extension device. The first host accesses a memory space of a memory of the second host through the first memory extension device and the second memory extension device according to a first physical address of the first host.
-
公开(公告)号：US20240045975A1
公开(公告)日：2024-02-08
申请号：US18066207
申请日：2022-12-14
发明人： SHUANGCHEN LI , ZHE ZHANG , LINYONG HUANG , DIMIN NIU , XUANLE REN , HONGZHONG ZHENG
CPC分类号： G06F21/602 , G06F21/54
摘要： The present disclosure discloses a processor and a multi-core processor. The processor includes a processor core and a memory. The processor core includes a homomorphic encryption instruction execution module and a general-purpose instruction execution module; the homomorphic encryption instruction execution module is configured to perform homomorphic encryption operation and includes a plurality of instruction set architecture extension components, wherein the plurality of instruction set architecture extension components are respectively configured to perform a sub-operation related to the homomorphic encryption; the general-purpose instruction execution module is configured to perform non-homomorphic encryption operation. The memory is vertically stacked with the processor core and is used as a cache or scratchpad memory of the processor core.
-
公开(公告)号：US20240069755A1
公开(公告)日：2024-02-29
申请号：US18064500
申请日：2022-12-12
发明人： YIJIN GUAN , TIANCHAN GUAN , DIMIN NIU , HONGZHONG ZHENG
CPC分类号： G06F3/0622 , G06F1/1632 , G06F3/0607 , G06F3/0632 , G06F3/0683
摘要： The present application provides a computer system, a memory expansion device and a method for use in the computer system. The computer system includes multiple hosts and multiple memory expansion devices; the memory expansion devices correspond to the hosts in a one-to-one manner. Each host includes a CPU and a memory; each memory expansion device includes a first interface and multiple second interfaces. The first interface is configured to allow each memory expansion device to communicate with the corresponding CPU via a first coherence interconnection protocol, and the second interface is configured to allow each memory expansion device to communicate with a portion of memory expansion devices via a second coherence interconnection protocol. Any two memory expansion devices communicate with each other via at least two different paths, and the number of memory expansion devices that at least one of the two paths passes through is not more than one.
-
公开(公告)号：US20240069754A1
公开(公告)日：2024-02-29
申请号：US18064451
申请日：2022-12-12
发明人： TIANCHAN GUAN , YIJIN GUAN , DIMIN NIU , HONGZHONG ZHENG
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0607 , G06F3/0631 , G06F3/0683
摘要： The present application discloses a computing system and an associated method. The computing system includes a first host, a second host, a first memory extension device and a second memory extension device. The first host includes a first memory, and the second host includes a second memory. The first host has a plurality of first memory addresses corresponding to a plurality of memory spaces of the first memory, and a plurality of second memory addresses corresponding to a plurality of memory spaces of the second memory. The first memory extension device is coupled to the first host. The second memory extension device is coupled to the second host and the first memory extension device. The first host accesses the plurality of memory spaces of the second memory through the first memory extension device and the second memory extension device.
-
公开(公告)号：US20240095179A1
公开(公告)日：2024-03-21
申请号：US18065123
申请日：2022-12-13
发明人： DIMIN NIU , YIJIN GUAN , TIANCHAN GUAN , SHUANGCHEN LI , HONGZHONG ZHENG
IPC分类号： G06F12/1009 , G06F12/0873 , G06F12/122
CPC分类号： G06F12/1009 , G06F12/0873 , G06F12/122
摘要： A memory management method of a data processing system is provided. The memory management method includes: creating a first memory zone and a second memory zone related to a first node of a first server, wherein the first server is located in the data processing system, and the first node includes a processor and a first memory; mapping the first memory zone to the first memory; and mapping the second memory zone to a second memory of a second server, wherein the second server is located in the data processing system, and the processor is configured to access the second memory of the second server through an interface circuit of the first server and through an interface circuit of the second server.
-
公开(公告)号：US20240094922A1
公开(公告)日：2024-03-21
申请号：US18064919
申请日：2022-12-12
发明人： DIMIN NIU , TIANCHAN GUAN , YIJIN GUAN , SHUANGCHEN LI , HONGZHONG ZHENG
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0683
摘要： A data processing system includes a first server and a second server. The first server includes a first processor group, a first memory space and a first interface circuit. The second server includes a second processor group, a second memory space and a second interface circuit. The first memory space and the second memory space are allocated to the first processor group. The first processor group is configured to perform memory error detection to generate an error log corresponding to a memory error. When the memory error occurs in the second memory space, the first interface circuit is configured to send the error log to the second interface circuit, and the second processor group is configured to log the memory error according to the error log received by the second interface circuit. The data processing system is capable of realizing memory reliability architecture supporting operations across different servers.
-
公开(公告)号：US20240054096A1
公开(公告)日：2024-02-15
申请号：US18064520
申请日：2022-12-12
发明人： SHUANGCHEN LI , ZHE ZHANG , DIMIN NIU , HONGZHONG ZHENG
IPC分类号： G06F15/173 , G06F15/78 , G06F12/0813
CPC分类号： G06F15/17381 , G06F15/7825 , G06F12/0813
摘要： The present disclosure discloses a processor. The processor is used to perform parallel computation and includes a logic die and a memory die. The logic die includes a plurality of processor cores and a plurality of networks on chip, wherein each processor core is programmable. The plurality of networks on chip are correspondingly connected to the plurality of processor cores, so that the plurality of processor cores form a two-dimensional mesh network. The memory die and the processor core are stacked vertically, wherein the memory die includes a plurality of memory tiles, and when the processor performs the parallel computation, the plurality of memory tiles do not have cache coherency; wherein, the plurality of memory tiles correspond to the plurality of processor cores in a one-to-one or one-to-many manner.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.013 秒)
