公开(公告)号：US20150253372A1

公开(公告)日：2015-09-10

申请号：US14634495

申请日：2015-02-27

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Takuya WATANABE ,  Shuji YANAGI ,  Shinya YOKOYAMA ,  Toshiyuki OKI ,  Akira ASAO

IPC: G01R31/04 ,  G01N27/22 ,  G01R31/02 ,  G01R27/26

CPC classification number: G01R31/041 ,  G01N27/223 ,  G01N27/228 ,  G01R27/2605 ,  G01R31/024 ,  G01R31/2829 ,  H01L2221/00 ,  H04L1/00 ,  H04L2201/00

Abstract: In a reset period of a first stage, a switching circuit is turned on, and high-level driving voltages are output from driving circuits. In a charge transfer period subsequent to the reset period, the switching circuit is turned off, and low-level driving voltages are output from the driving circuits. It is determined whether or not an output voltage of an amplifier circuit in the charge transfer period is included in a normal range. In the inspection of a second stage subsequent to the first stage, in the same manner as in the normal measurement, voltages having opposite phases are output from the driving circuits in the reset period and the charge transfer period, and it is determined whether or not the output voltage of the amplifier circuit in the charge transfer period is included in a normal range.

Abstract translation: 在第一级的复位期间，开关电路导通，高电平驱动电压从驱动电路输出。 在复位周期之后的电荷转移期间，切换电路被断开，低电平驱动电压从驱动电路输出。 确定电荷转移期间的放大电路的输出电压是否包含在正常范围内。 在第一阶段之后的第二阶段的检查中，以与正常测量相同的方式，在复位周期和电荷转移期间，从驱动电路输出具有相反相位的电压，并且确定是否 电荷转移期间的放大电路的输出电压被包含在正常范围内。

公开(公告)号：US20180234085A1

公开(公告)日：2018-08-16

申请号：US15950327

申请日：2018-04-11

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Akira ASAO ,  Kiyoshi SASAI ,  Tatsumi FUJIYOSHI

IPC: H03K3/012 ,  H03K5/00 ,  G06F3/044 ,  G06F3/041

CPC classification number: H03K3/012 ,  G06F1/02 ,  G06F3/0416 ,  G06F3/044 ,  G06F7/16 ,  G06G7/16 ,  H03K5/00006

Abstract: In a sine-wave multiplier, signal components included in an output signal Qu1 and corresponding to the product of a third-order harmonic component of a first square wave W1 and an input signal Vi and the product of a fifth-order harmonic component of the first square wave W1 and the input signal Vi are offset by a signal component included in an output signal Qu2 and corresponding to the product of a fundamental component of a second square wave W2 and the input signal Vi and a signal component included in an output signal Qu3 and corresponding to the product of a fundamental component of a second square wave W3 and the input signal Vi.

公开(公告)号：US20150256166A1

公开(公告)日：2015-09-10

申请号：US14634464

申请日：2015-02-27

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Junichi SAITO ,  Akira ASAO ,  Tomoyuki SAWATAISHI

IPC: H03K5/1532

CPC classification number: H03K5/1532

Abstract: The highest voltage of a power supply voltage, a ground potential, and a signal voltage is output as a selection voltage from a terminal on the output side. In this case, terminals on the input side and the terminal on the output side are connected to each other through MOS transistors in the ON state. Therefore, it is possible to suppress a voltage drop due to a parasitic diode of each MOS transistor.

Abstract translation: 从输出侧的端子输出电源电压，接地电位和信号电压的最高电压作为选择电压。 在这种情况下，输入侧的端子和输出侧的端子通过处于导通状态的MOS晶体管彼此连接。 因此，可以抑制由于每个MOS晶体管的寄生二极管引起的电压降。