公开(公告)号：US20150256166A1

公开(公告)日：2015-09-10

申请号：US14634464

申请日：2015-02-27

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Junichi SAITO ,  Akira ASAO ,  Tomoyuki SAWATAISHI

IPC: H03K5/1532

CPC classification number: H03K5/1532

Abstract: The highest voltage of a power supply voltage, a ground potential, and a signal voltage is output as a selection voltage from a terminal on the output side. In this case, terminals on the input side and the terminal on the output side are connected to each other through MOS transistors in the ON state. Therefore, it is possible to suppress a voltage drop due to a parasitic diode of each MOS transistor.

Abstract translation: 从输出侧的端子输出电源电压，接地电位和信号电压的最高电压作为选择电压。 在这种情况下，输入侧的端子和输出侧的端子通过处于导通状态的MOS晶体管彼此连接。 因此，可以抑制由于每个MOS晶体管的寄生二极管引起的电压降。

公开(公告)号：US20150244318A1

公开(公告)日：2015-08-27

申请号：US14603189

申请日：2015-01-22

Applicant: ALPS ELECTRIC CO., LTD.

Inventor： Junichi SAITO ,  Kimihiro NAKAO

IPC: H03B5/02

CPC classification number: H03B5/364

Abstract: When an external clock signal exceeding a power supply voltage is input to a first terminal, a voltage of a bulk of a P type MOS transistor becomes higher than a power supply voltage, but a current does not flow from the bulk of the P type MOS transistor to a first power supply line since a first diode is provided in a forward direction with respect to a direction of a current flowing from a first power supply line to the bulk of the P type MOS transistor. Therefore, it is possible to reliably prevent a reverse current from flowing from the first terminal to the first power supply line.

Abstract translation: 当超过电源电压的外部时钟信号被输入到第一端子时，P型MOS晶体管的体积的电压变得高于电源电压，但是电流不从P型MOS的大部分流出 由于第一二极管相对于从第一电源线流向P型MOS晶体管的主体的电流的方向在正向方向上被提供，所以是第一电源线。 因此，可以可靠地防止反向电流从第一端子流到第一电源线。