公开(公告)号：US20240195421A1

公开(公告)日：2024-06-13

申请号：US18415692

申请日：2024-01-18

申请人： AMLOGIC (SHANGHAI) CO., LTD.

发明人： Yang Yang ,  Xu Guo

IPC分类号： H03L7/081 ,  H03L7/099

CPC分类号： H03L7/0818 ,  H03L7/0992

摘要： The present disclosure discloses a clock signal noise reduction device and noise reduction method, and a multi-phase delay phase-locked loop. The clock signal noise reduction device includes a phase generator, a phase selector, and a frequency divider. The phase generator is configured to generate a multi-phase clock signal based on an input signal. The phase selector has an input end connected with an output end of the phase generator, and is configured to select a channel of the multi-phase clock signal based on phase information and assign a delay of a preset period to a clock signal of the selected channel. The preset period is less than a cycle period of the multi-phase clock signal. The frequency divider has an input end connected to an output end of the phase selector, and is configured to perform fractional frequency division on the multi-phase clock signal delayed by the preset period.