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公开(公告)号：US12128106B2
公开(公告)日：2024-10-29
申请号：US18584914
申请日：2024-02-22
发明人： Mark George Saulnier , Jesse Jingyang Chen , Srinivasa Karra , Kevin Tyler Sprott , Jason Allan Wiles , Soumya Ray
IPC分类号： A61K47/54 , A61K47/62 , C07H5/06 , C07H7/02 , C07H9/02 , C07H9/04 , C07H15/203 , C07H17/00 , C07H17/02 , C07H19/02 , C07H19/044 , H03L7/081 , H03L7/099
CPC分类号： A61K47/549 , A61K47/62 , C07H5/06 , C07H7/02 , C07H9/02 , C07H9/04 , C07H15/203 , C07H17/00 , C07H17/02 , C07H19/02 , C07H19/044 , H03L7/0814 , H03L7/0818 , H03L7/0998
摘要： Compounds and compositions that have an asialoglycoprotein receptor (ASGPR) binding ligand bound to an extracellular protein binding ligand for the selective degradation of the target extracellular protein in vivo to treat disorders mediated by the extracellular protein are described.
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2.发明授权公开(公告)号：US12119830B2
公开(公告)日：2024-10-15
申请号：US18120819
申请日：2023-03-13
申请人： Apple Inc.
发明人： Jongmin Park , Karim M Megawer , Thomas Mayer
CPC分类号： H03L7/083 , H03L7/0818 , H03L7/195
摘要： This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.
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公开(公告)号：US12063043B2
公开(公告)日：2024-08-13
申请号：US18170088
申请日：2023-02-16
申请人： MEDIATEK INC.
发明人： Guan-Yu Su
CPC分类号： H03L7/0818 , H03L7/0998 , H03L7/1806
摘要： A clock scheme circuit with low power consumption is shown. A local clock generator is coupled to a global clock generator through a global clock trace to receive a global clock signal, and generate a local clock signal based on the global clock signal. The local clock generator uses a frequency multiplier to multiply the frequency of the global clock signal by a multiplication factor of not less than 1. Thus, the global clock signal transferred through the global clock trace can be a lower-frequency signal in comparison with the local clock signal. The power consumption along the global clock trace is considerably reduced.
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公开(公告)号：US12057846B2
公开(公告)日：2024-08-06
申请号：US18301299
申请日：2023-04-17
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/095
摘要： Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.
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公开(公告)号：US20240233809A1
公开(公告)日：2024-07-11
申请号：US18519679
申请日：2023-11-27
发明人： Shinya OKUNO
IPC分类号： G11C11/4076 , G11C11/4096 , H03L7/081
CPC分类号： G11C11/4076 , G11C11/4096 , H03L7/0818
摘要： A control circuit includes a control unit, a delay line unit, and a detection unit. The delay line unit delays an input clock signal based on the delay amount and generates an output clock signal. The detection unit performs a detection operation to detect the number of delayed clock cycles from the input clock signal to the output clock signal. The control unit changes the delay amount during a delay operation and controls the delay line unit so that the input clock signal is synchronized with the output clock signal. Before the delay operation, the detection unit performs the detection operation multiple times and detects a plurality of numbers of delayed clock cycles. The control unit sets the delay amount for the detection operation and sets the delay amount for the delay operation according to plurality of detected numbers of delayed clock cycles.
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公开(公告)号：US12028079B2
公开(公告)日：2024-07-02
申请号：US18115682
申请日：2023-02-28
CPC分类号： H03L7/0818 , H03L7/0814 , H03L7/0816 , H03L7/085
摘要： An example apparatus includes: digitally locked loop (DLL) circuitry coupled to a clock terminal and configured to generate a plurality of delayed clocks at a plurality of delayed clock terminals based on a reference clock of the clock terminal; first retimer circuitry coupled to the plurality of delayed clock terminals, a first data terminal, and a second data terminal, the first retimer circuitry configured to delay and serialize data of the first data terminal and the second data terminal using at least one of the delayed clocks of the plurality of delayed clock terminals; and second retimer circuitry coupled to the plurality of delayed clock terminals, a third data terminal, and a fourth data terminal, the second retimer circuitry configured to delay and serialize data of the third data terminal and the fourth data terminal.
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公开(公告)号：US12019464B2
公开(公告)日：2024-06-25
申请号：US17552318
申请日：2021-12-15
CPC分类号： G06F1/10 , H01L25/0657 , H03L7/00 , H03L7/0816 , H03L7/0818 , H03L7/083 , H03L7/0991 , H01L2924/18161
摘要： A semiconductor package includes source clock circuitry to generate a source clock signal. Reference clock circuitry generates a reference clock signal. A first timing circuit includes a first source clock input to receive the source clock signal. First fan-out circuitry distributes the received source clock signal as a first distributed clock signal to a first set of clocked devices. A first delay circuit delays the received source clock signal by a first delay value based on a first phase difference between the first distributed clock signal and the reference clock signal.
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8.发明公开公开(公告)号：US20240195421A1
公开(公告)日：2024-06-13
申请号：US18415692
申请日：2024-01-18
CPC分类号： H03L7/0818 , H03L7/0992
摘要： The present disclosure discloses a clock signal noise reduction device and noise reduction method, and a multi-phase delay phase-locked loop. The clock signal noise reduction device includes a phase generator, a phase selector, and a frequency divider. The phase generator is configured to generate a multi-phase clock signal based on an input signal. The phase selector has an input end connected with an output end of the phase generator, and is configured to select a channel of the multi-phase clock signal based on phase information and assign a delay of a preset period to a clock signal of the selected channel. The preset period is less than a cycle period of the multi-phase clock signal. The frequency divider has an input end connected to an output end of the phase selector, and is configured to perform fractional frequency division on the multi-phase clock signal delayed by the preset period.
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公开(公告)号：US11990913B2
公开(公告)日：2024-05-21
申请号：US18079424
申请日：2022-12-12
申请人： Apple Inc.
发明人： Chen Zhai , Abbas Komijani
CPC分类号： H03L7/0818 , H03L7/085
摘要： To increase the operating frequency range of the DLL while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (DLL). The DLL may include a voltage-controlled delay line (VCDL) including multiple switched capacitors coupled in parallel to each other. An electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. The coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the VCDL, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. Such a DLL implementation may increase DLL tuning range and decrease phase noise, among other advantages.
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公开(公告)号：US20240106440A1
公开(公告)日：2024-03-28
申请号：US18079424
申请日：2022-12-12
申请人： Apple Inc.
发明人： Chen Zhai , Abbas Komijani
CPC分类号： H03L7/0818 , H03L7/085
摘要： To increase the operating frequency range of the DLL while decreasing varactor sizes, coarse tuning circuitry may be implemented in a delay-locked loop (DLL). The DLL may include a voltage-controlled delay line (VCDL) including multiple switched capacitors coupled in parallel to each other. An electrical ground may be coupled to the parallel switched capacitors at a first node and a buffer and variable capacitor may be coupled to the parallel switched capacitors at a second node. The coarse tuning circuitry may be electrically coupled to a phase detector and to the multiple switched capacitors of the VCDL, such that the coarse tuning circuitry may receive a signal (e.g., an indication of a phase) from the phase detector and may adjust switched capacitor loading based on the signal received from the phase detector. Such a DLL implementation may increase DLL tuning range and decrease phase noise, among other advantages.
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