公开(公告)号：US20170146643A1

公开(公告)日：2017-05-25

申请号：US15352760

申请日：2016-11-16

Applicant: Analog Devices, Inc.

Inventor： ERIC G. NESTLER

IPC: G01S7/52 ,  A61B8/00 ,  A61B8/08 ,  A61B8/06

CPC classification number: G01S7/52047 ,  A61B8/06 ,  A61B8/4483 ,  A61B8/5207 ,  A61B8/5215 ,  G01S7/52003 ,  G01S7/52095 ,  G01S15/8915 ,  G01S15/8927 ,  G01S15/8997 ,  G10K11/346

Abstract: A sampled analog beamformer for ultrasound beamforming includes an array of transducers for transmitting analog signals and receiving reflected analog signals, and a sampled analog filter for filtering the received reflected analog. The sampled analog filter includes a delay line for adding a delay to each of the received reflected analog signals. Using a sampled analog filter in an ultrasound beamforming system reduces the power usage of the system and decreases the number of components in the system.

公开(公告)号：US20160097846A1

公开(公告)日：2016-04-07

申请号：US14875022

申请日：2015-10-05

Applicant: ANALOG DEVICES, INC.

Inventor： MIKAEL MORTENSEN ,  ERIC G. NESTLER ,  J. BRIAN HARRINGTON ,  JEFFREY G. BERNSTEIN

IPC: G01S7/52

CPC classification number: G01S7/52017 ,  G01S7/52034 ,  G01S7/5208 ,  G01S15/8915 ,  G10K11/346

Abstract: A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers.

Abstract translation: 提供了一种用于超声波波束形成的系统，包括采样的模拟波束形成器，超声波换能器的阵列以及耦合到采样的模拟波束形成器和超声换能器阵列的高压放大器。 采样的模拟波束形成器包括一个采样的模拟滤波器，用于对输入的模拟信号进行滤波，并增加分数延迟，并传输滤波的模拟超声信号。 超声波换能器的阵列进一步发射经滤波的模拟超声信号。 高压放大器驱动超声波换能器阵列中的换能器。

公开(公告)号：US20150372682A1

公开(公告)日：2015-12-24

申请号：US14745017

申请日：2015-06-19

Applicant: ANALOG DEVICES, INC.

Inventor： ALEXANDER A. ALEXEYEV ,  ERIC G. NESTLER

IPC: H03L7/08

CPC classification number: H03L7/085

Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.

Abstract translation: 集成电路实现了锁相环（PLL）的至少一部分。 集成电路包括用于PLL的采样模拟环路滤波器。 环路滤波器包括用于接收表示参考时钟信号和第一时钟信号之间的相位差的信号的第一输入端，用于提供用于控制振荡器频率的频率控制信号的第一输出端，​​用于接收振荡器的时钟输入 环路定时时钟信号，用于控制环路滤波器的操作定时;以及数字控制输入，用于根据多个控制值配置环路滤波器的响应。 在一些示例中，环路滤波器包括通过可控开关耦合的电荷存储元件和用于在电荷存储元件之间传送电荷的控制电路，以产生环路滤波器的配置响应。