公开(公告)号：US20160350240A1

公开(公告)日：2016-12-01

申请号：US14726190

申请日：2015-05-29

Applicant: ANALOG DEVICES GLOBAL

Inventor： Richard F. Grafton ,  Shivakumar Patil ,  James Potts ,  Lewis F. Lahr

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F13/4282

Abstract: A serial peripheral interface (SPI) host port is disclosed that enables a host external to a processor to access the processor's memory-mapped resources using SPI memory command protocol. An exemplary processor can include a system interconnect connected to memory-mapped resources and a SPI host port connected to the system interconnect. The SPI host port is configured to use SPI memory command protocol to access memory-mapped resources of the processor for the host external to the processor.

Abstract translation: 公开了一种串行外设接口（SPI）主机端口，使得处理器外部的主机能够使用SPI存储器命令协议访问处理器的存储器映射资源。 示例性处理器可以包括连接到存储器映射资源的系统互连和连接到系统互连的SPI主机端口。 SPI主机端口配置为使用SPI存储器命令协议来访问处理器外部处理器的内存映射资源。

公开(公告)号：US20160349326A1

公开(公告)日：2016-12-01

申请号：US14721152

申请日：2015-05-26

Applicant: ANALOG DEVICES GLOBAL

Inventor： Richard F. Grafton ,  Chad R. Wentworth ,  Yashwanth Nagaraja

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31705

Abstract: A system, such as a system-on-chip, has a non-debug domain and a debug domain. The debug domain has a debug framework that enables a debugger driven, non-debug domain system reset. The system includes a reset control unit, and a debug trigger mechanism that includes a debug trigger interface (DTI) connected to the reset control unit. The DTI is configured to trigger the reset control unit to reset the non-debug domain. The DTI may further be configured to monitor a status of the non-debug domain system reset.

Abstract translation: 诸如片上系统的系统具有非调试域和调试域。 调试域具有调试框架，可以调试器驱动，非调试域系统重置。 该系统包括复位控制单元和调试触发机制，其包括连接到复位控制单元的调试触发接口（DTI）。 DTI配置为触发复位控制单元以重置非调试域。 还可以将DTI配置为监视非调试域系统重置的状态。