公开(公告)号：US20140074901A1

公开(公告)日：2014-03-13

申请号：US14055177

申请日：2013-10-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andreas D. Olofsson ,  Baruch Yanovitch

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06F7/5324 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3885

Abstract: Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of to the second operands from the compute register file to respective multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the local operand register to respective multipliers, to supply the second operands from the compute register file to respective multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein one or more of the first operands in the local operand register are reused by the multipliers in two or more multiplication operations.

Abstract translation: 为数字处理器提供乘法引擎和乘法方法。 乘法引擎包括乘法器，每个乘法器接收第一操作数和第二操作数; 本地操作数寄存器，其具有用于保持各乘法器的第一操作数的位置; 耦合到本地操作数寄存器的第一操作数总线，用于将第一操作数从计算寄存器文件提供给本地操作数寄存器; 耦合到所述多个乘法器的第二操作数总线，以将所述第二操作数中的一个或多个从计算寄存器文件提供给各个乘法器; 以及控制单元，其响应于数字处理器指令将第一操作数从本地操作数寄存器提供给各个乘法器，以将第二操作数从计算寄存器文件提供给第二操作数总线上的相应乘法器，并将第一操作数乘以 各个乘法器中的相应的第二操作数，其中本地操作数寄存器中的第一操作数中的一个或多个在两个或多个乘法运算中由乘法器重新使用。