公开(公告)号：US20160267964A1

公开(公告)日：2016-09-15

申请号：US15013687

申请日：2016-02-02

申请人： ANNA Y. HERR ,  QUENTIN P. HERR ,  ANDREW HOSTETLER MIKLICH

发明人： ANNA Y. HERR ,  QUENTIN P. HERR ,  ANDREW HOSTETLER MIKLICH

IPC分类号： G11C11/44

CPC分类号： G11C11/44 ,  G11C11/16

摘要： One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state. The memory cell also includes a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell. The memory cell further includes at least one Josephson junction configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state.

摘要翻译： 一个实施例描述了一个存储单元。 存储器单元包括相滞后磁约瑟夫逊结（PHMJJ），其被配置为存储对应于二进制逻辑1状态的第一二进制逻辑状态和对应于二进制逻辑0状态的第二二进制逻辑状态之一，以响应于 写入电流，其被提供给存储器单元并且基于所存储的数字状态生成超导相位。 存储器单元还包括超导读取选择器件，其被配置为响应于提供给存储器单元的读取电流来实现读取操作。 存储单元还包括至少一个约瑟夫逊结，其被配置为在读取操作期间基于PHMJJ的超导相位提供输出，对应于所存储的数字状态的输出。