公开(公告)号：US20140201547A1

公开(公告)日：2014-07-17

申请号：US13741443

申请日：2013-01-15

Applicant: APPLE INC.

Inventor： Abhijeet R. Tanpure ,  Alexander E. Runas

IPC: G06F1/32 ,  G11C7/22

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2227 ,  Y02D10/13 ,  Y02D10/14

Abstract: Embodiments of a memory device are disclosed that may allow for detecting the opportunity for energy savings and implementing the energy savings for each access to the memory device. The memory device may include a plurality of columns, an address comparator, and a timing and control circuit. Each of the plurality of columns may include a plurality of data storage cells coupled to a common data line, and a pre-charge circuit that may be configured to charge the common data line to a pre-determined voltage. The address comparator may be configured to compare an address value to a previous address value, and generate an output dependent upon the comparison. The timing and control circuit may then selectively disable pre-charge circuits in the plurality of columns dependent upon the generated output of the address comparator.

Abstract translation: 公开了一种存储器件的实施例，其可以允许检测节能的机会并且实现对存储器件的每次访问的节能。 存储器件可以包括多个列，地址比较器，以及定时和控制电路。 多个列中的每一个可以包括耦合到公共数据线的多个数据存储单元和可以被配置为将公共数据线充电到预定电压的预充电电路。 地址比较器可以被配置为将地址值与先前地址值进行比较，并且根据比较生成输出。 然后，定时和控制电路可以根据所产生的地址比较器的输出来选择性地禁用多列中的预充电电路。