公开(公告)号：US10742278B2

公开(公告)日：2020-08-11

申请号：US15763860

申请日：2015-10-30

Applicant: Apple Inc.

Inventor： Farhana Sheikh ,  Alexios Konstantinos Balatsoukas Stimming

IPC: H04B7/0456 ,  H04B7/0413 ,  H04B7/08 ,  H04L27/26

Abstract: An orthogonalization matrix calculation circuit may include a scaling coefficient calculation circuit configured to calculate a scaling coefficient for each of a plurality of candidate update operations for the orthogonalization matrix, wherein each of the plurality of candidate update operations comprises combining linearly at least one of a first column or a second column of the orthogonalization matrix previously utilized to update the orthogonalization matrix, an update operation selection circuit configured to select an optimum candidate update operation from the plurality of candidate update operations, and a matrix update circuit configured to update the orthogonalization matrix according to the scaling coefficient of the optimum candidate update operation.

公开(公告)号：US20220407549A1

公开(公告)日：2022-12-22

申请号：US17893647

申请日：2022-08-23

Applicant: Apple Inc.

Inventor： Oner Orhan ,  Hosein Nikopour ,  Peter Sagazio ,  Farhana Sheikh ,  Junyoung Nam ,  Shilpa Talwar

IPC: H04B1/16

Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.

公开(公告)号：US12184316B2

公开(公告)日：2024-12-31

申请号：US17893647

申请日：2022-08-23

Applicant: Apple Inc.

Inventor： Oner Orhan ,  Hosein Nikopour ,  Peter Sagazio ,  Farhana Sheikh ,  Junyoung Nam ,  Shilpa Talwar

IPC: H04B1/16

Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.

公开(公告)号：US11444645B2

公开(公告)日：2022-09-13

申请号：US16958813

申请日：2018-01-02

Applicant: APPLE INC.

Inventor： Oner Orhan ,  Hosein Nikopour ,  Peter Sagazio ,  Farhana Sheikh ,  Junyoung Nam ,  Shilpa Talwar

IPC: H04B1/16

Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.