公开(公告)号：US08797082B2

公开(公告)日：2014-08-05

申请号：US13629919

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Ravi K. Ramaswami ,  Geertjan Joordens

IPC: H03K3/00

CPC classification number: H03K23/42

Abstract: A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement.

Abstract translation: 一种用于低速输入/输出引脚有效地执行高速时钟信号定时表征的系统和方法。 集成电路包括产生高速时钟信号的时钟发生器。 时钟表征器电路接收高速时钟信号。 时钟表征器产生相应的低速时钟信号。 生成的低速时钟信号通过低速通用输入/输出（GPIO）引脚输出进行测量。 生成的低速时钟信号被发送到用于分段的顺序元件。 所产生的低速时钟信号的分级由使用与前一级使用的极性相反的时钟信号的顺序元件完成。 高速时钟信号用于分段。 每个级的输出发送到低速GPIO引脚进行测量。

公开(公告)号：US20150046763A1

公开(公告)日：2015-02-12

申请号：US13964463

申请日：2013-08-12

Applicant: Apple Inc.

Inventor： Samy R. Makar ,  Jianlin Yu ,  Ravi K. Ramaswami

IPC: G01R31/3177

CPC classification number: G01R31/318555

Abstract: An apparatus and method for controlling a test controller is disclosed. An apparatus includes test controllers of a first type configured to operate according to a first protocol and test controllers of a second type configured to operate according to a second protocol. A test controller of the second type may be associated with one of the test controllers of the first type, with the former controlling the latter. The test controllers of the second type may each control associated ones of the test controllers of the second type in parallel and independently of one another.

Abstract translation: 公开了一种用于控制测试控制器的装置和方法。 一种装置包括被配置为根据第一协议操作的第一类型的测试控制器和被配置为根据第二协议操作的第二类型的测试控制器。 第二类型的测试控制器可以与第一类型的测试控制器中的一个相关联，前者控制后者。 第二类型的测试控制器可以彼此并行并且彼此独立地控制第二类型的测试控制器中的相关联的测试控制器。

公开(公告)号：US20140091841A1

公开(公告)日：2014-04-03

申请号：US13629919

申请日：2012-09-28

Applicant: APPLE INC.

Inventor： Ravi K. Ramaswami ,  Geertjan Joordens

IPC: H03K23/42

CPC classification number: H03K23/42

Abstract: A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement.

Abstract translation: 一种用于低速输入/输出引脚有效地执行高速时钟信号定时表征的系统和方法。 集成电路包括产生高速时钟信号的时钟发生器。 时钟表征器电路接收高速时钟信号。 时钟表征器产生相应的低速时钟信号。 生成的低速时钟信号通过低速通用输入/输出（GPIO）引脚输出进行测量。 生成的低速时钟信号被发送到用于分段的顺序元件。 所产生的低速时钟信号的分级由使用与前一级使用的极性相反的时钟信号的顺序元件完成。 高速时钟信号用于分段。 每个级的输出发送到低速GPIO引脚进行测量。