公开(公告)号：US09679891B2

公开(公告)日：2017-06-13

申请号：US14220293

申请日：2014-03-20

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Xiaofeng Fan ,  Geertjan Joordens

IPC: H01L27/02 ,  H02H3/20 ,  H02H3/22 ,  H02H9/04

CPC classification number: H01L27/0285 ,  H02H3/20 ,  H02H3/22 ,  H02H9/046

Abstract: ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.

公开(公告)号：US08797082B2

公开(公告)日：2014-08-05

申请号：US13629919

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Ravi K. Ramaswami ,  Geertjan Joordens

IPC: H03K3/00

CPC classification number: H03K23/42

Abstract: A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement.

Abstract translation: 一种用于低速输入/输出引脚有效地执行高速时钟信号定时表征的系统和方法。 集成电路包括产生高速时钟信号的时钟发生器。 时钟表征器电路接收高速时钟信号。 时钟表征器产生相应的低速时钟信号。 生成的低速时钟信号通过低速通用输入/输出（GPIO）引脚输出进行测量。 生成的低速时钟信号被发送到用于分段的顺序元件。 所产生的低速时钟信号的分级由使用与前一级使用的极性相反的时钟信号的顺序元件完成。 高速时钟信号用于分段。 每个级的输出发送到低速GPIO引脚进行测量。

公开(公告)号：US20140173313A1

公开(公告)日：2014-06-19

申请号：US13717941

申请日：2012-12-18

Applicant: APPLE INC.

Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S. Thiara

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G09G5/00 ,  G09G5/006 ,  G09G5/18 ,  G09G2330/021 ,  G09G2370/10

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路和辅助链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令，辅助链路可指示主链路上的频率变化。 通过主链路到宿处理器的源处理器可以发送初始化参数，其可以包括时钟数据恢复锁定参数和空闲参数。

公开(公告)号：US09541603B2

公开(公告)日：2017-01-10

申请号：US13938901

申请日：2013-07-10

Applicant: Apple Inc.

Inventor： Brian S. Park ,  Patrick D. McNamara ,  Kwang M. Lee ,  Meng C. Chong ,  Geertjan Joordens ,  Raman S. Thiara ,  Anh T. Hoang ,  John P. Gonzalez

IPC: G01R31/00 ,  G01R31/317 ,  G01R19/165 ,  G06F1/28 ,  G01R31/3181

CPC classification number: G01R31/31721 ,  G01R19/16552 ,  G01R31/31816 ,  G06F1/28

Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

Abstract translation: 公开了一种用于IC中电源故障检测的方法和装置。 在一个实施例中，一种方法包括检测电压瞬变的IC中的检测电路，其中电源电压的值至少暂时低于参考电压值。 响应于此，检测电路可以使逻辑值存储在指示检测电路已经检测到低于参考电压的电源电压的寄存器中。 IC可以包括耦合到寄存器的多个检测电路，每个检测电路可以提供检测低于参考电压的电源电压的相应指示。 检测电路可以放置在不同的位置，因此读取寄存器可以产生指示出现这种电压瞬变的位置（如果有的话）的信息。

公开(公告)号：US20150270258A1

公开(公告)日：2015-09-24

申请号：US14220293

申请日：2014-03-20

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Xiaofeng Fan ,  Geertjan Joordens

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0285 ,  H02H3/20 ,  H02H3/22 ,  H02H9/046

Abstract: ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.

Abstract translation: 公开了ESD保护电路。 在一个实施例中，集成电路包括第一和第二传感器电路。 第一传感器电路具有第一电阻 - 电容（RC）时间常数，而第二传感器电路具有第二RC时间常数。 第一传感器电路的RC时间常数比第二传感器电路的RC时间常数至少大一个数量级。 第一钳位晶体管耦合到并被配置为由第一传感器电路激活，响应于后者检测ESD事件。 第二钳位晶体管被耦合到并被配置为由第二传感器电路激活，响应于后者检测ESD事件。

公开(公告)号：US09158350B2

公开(公告)日：2015-10-13

申请号：US13717941

申请日：2012-12-18

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S Thiara

IPC: G06F1/26 ,  G09G5/00

CPC classification number: G06F1/26 ,  G09G5/00 ,  G09G5/006 ,  G09G5/18 ,  G09G2330/021 ,  G09G2370/10

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路和辅助链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令，辅助链路可指示主链路上的频率变化。 通过主链路到宿处理器的源处理器可以发送初始化参数，其可以包括时钟数据恢复锁定参数和空闲参数。

公开(公告)号：US09013493B2

公开(公告)日：2015-04-21

申请号：US13718142

申请日：2012-12-18

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S Thiara

IPC: G06F13/14 ,  G06F15/00 ,  G06F15/16 ,  G09G5/00

CPC classification number: G09G5/00 ,  G09G5/006

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 源处理器可以可操作以从连续的频率范围中选择频率，并且以选定的频率将数据发送到宿处理器。 在宿处理器中可以包括锁相电路。 相位锁定电路可以被配置为根据发送的数据产生所选频率的信号。 产生的信号可以与发送的数据同相。

公开(公告)号：US20150015283A1

公开(公告)日：2015-01-15

申请号：US13938901

申请日：2013-07-10

Applicant: Apple Inc.

Inventor： Brian S. Park ,  Patrick D. McNamara ,  Kwang M. Lee ,  Meng C. Chong ,  Geertjan Joordens ,  Raman S. Thiara ,  Anh T. Hoang ,  John P. Gonzalez

IPC: G01R31/319

CPC classification number: G01R31/31721 ,  G01R19/16552 ,  G01R31/31816 ,  G06F1/28

Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

Abstract translation: 公开了一种用于IC中电源故障检测的方法和装置。 在一个实施例中，一种方法包括检测电压瞬变的IC中的检测电路，其中电源电压的值至少暂时低于参考电压值。 响应于此，检测电路可以使逻辑值存储在指示检测电路已经检测到低于参考电压的电源电压的寄存器中。 IC可以包括耦合到寄存器的多个检测电路，每个检测电路可以提供检测低于参考电压的电源电压的相应指示。 检测电路可以放置在不同的位置，因此读取寄存器可以产生指示出现这种电压瞬变的位置（如果有的话）的信息。

公开(公告)号：US20140168234A1

公开(公告)日：2014-06-19

申请号：US13718142

申请日：2012-12-18

Applicant: APPLE INC.

Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S. Thiara

IPC: G06T1/20

CPC classification number: G09G5/00 ,  G09G5/006

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 源处理器可以可操作以从连续的频率范围中选择频率，并且以选定的频率将数据发送到宿处理器。 在宿处理器中可以包括锁相电路。 相位锁定电路可以被配置为根据发送的数据产生所选频率的信号。 产生的信号可以与发送的数据同相。

公开(公告)号：US20140091841A1

公开(公告)日：2014-04-03

申请号：US13629919

申请日：2012-09-28

Applicant: APPLE INC.

Inventor： Ravi K. Ramaswami ,  Geertjan Joordens

IPC: H03K23/42

CPC classification number: H03K23/42

Abstract: A system and method for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins. An integrated circuit includes a clock generator that generates a high-speed clock signal. A clock characterizer circuit receives the high-speed clock signal. The clock characterizer generates a corresponding low-speed clock signal. The generated low-speed clock signal is output through a low-speed general-purpose input/output (GPIO) pin for measurement. The generated low-speed clock signal is sent to a sequential element for staging. The staging of the generated low-speed clock signal is done with sequential elements that use a reverse polarity of a clock signal than the polarity used by a previous stage. The high-speed clock signal is used for the staging. The output of each stage is sent to a low-speed GPIO pin for measurement.

Abstract translation: 一种用于低速输入/输出引脚有效地执行高速时钟信号定时表征的系统和方法。 集成电路包括产生高速时钟信号的时钟发生器。 时钟表征器电路接收高速时钟信号。 时钟表征器产生相应的低速时钟信号。 生成的低速时钟信号通过低速通用输入/输出（GPIO）引脚输出进行测量。 生成的低速时钟信号被发送到用于分段的顺序元件。 所产生的低速时钟信号的分级由使用与前一级使用的极性相反的时钟信号的顺序元件完成。 高速时钟信号用于分段。 每个级的输出发送到低速GPIO引脚进行测量。