公开(公告)号：US20140112429A1

公开(公告)日：2014-04-24

申请号：US13658115

申请日：2012-10-23

Applicant: APPLE INC.

Inventor： Ajay Bhatia ,  Greg M. Hess ,  Sanjay P. Zambare

IPC: G11C19/28

CPC classification number: G11C19/28 ,  G11C11/412 ,  G11C2207/007

Abstract: A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node. One or more PMOS transistors are coupled in series between the virtual voltage node and a global voltage node. Each of the one or more PMOS transistors includes a gate terminal that is hardwired to a ground node, and thus these devices remain active when power is applied to the global voltage node. The presence of the one or more PMOS devices coupled between the virtual and global voltage nodes results in the ability to overwrite contents stored in the state element at lower voltages than otherwise attainable without the one or more PMOS devices.

Abstract translation: 公开了一种用于实现较低电压写入的寄存器文件单元结构。 在一个实施例中，寄存器文件包括由两个交叉耦合的反相器组成的状态元件。 每个反相器包括具有耦合到虚拟电压节点的源极端子的p沟道金属氧化物半导体（PMOS）晶体管。 一个或多个PMOS晶体管串联耦合在虚拟电压节点和全局电压节点之间。 一个或多个PMOS晶体管中的每一个包括硬接线到接地节点的栅极端子，因此当向全局电压节点施加功率时，这些器件保持有效。 耦合在虚拟和全局电压节点之间的一个或多个PMOS器件的存在导致在没有一个或多个PMOS器件的情况下以比其它可获得的电压更低的电压来覆盖存储在状态元件中的内容的能力。