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公开(公告)号：US11803480B2
公开(公告)日：2023-10-31
申请号：US17662500
申请日：2022-05-09
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Ben D. Jarrett , Edward M. McCombs , Greg M. Hess
CPC classification number: G06F12/10 , G06F12/06 , G06F17/16 , G11C5/144 , G11C5/148 , G11C7/1006 , G11C8/06 , G11C11/419
Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
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公开(公告)号：US11418174B2
公开(公告)日：2022-08-16
申请号：US17245623
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Greg M. Hess , Vivekanandan Venugopal , Victor Zyuban
Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
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公开(公告)号：US10691610B2
公开(公告)日：2020-06-23
申请号：US16124166
申请日：2018-09-06
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Ben D. Jarrett , Edward M. McCombs , Greg M. Hess
Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
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4.发明申请公开(公告)号：US20190005993A1
公开(公告)日：2019-01-03
申请号：US15635825
申请日：2017-06-28
Applicant: Apple Inc.
Inventor： Bharan Giridhar , Sachmanik Cheema , Greg M. Hess
Abstract: A memory that includes multiple banks, each of which include multiple data storage cells, is disclosed. A decoder circuit may be configured to receive and decode information indicative of an address, and select a particular bank based on the decoded information. A first latch circuit coupled to a particular global bit line, which is, in turn, coupled to the particular bank, may generate multiple local clock signals using the decoded information and store data based on a voltage level of the particular global bit line using the plurality of local clock signals. Other circuits may also pre-charge the particular global bit line using a particular local clock signal of the plurality of local clock signals.
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公开(公告)号：US20190052254A1
公开(公告)日：2019-02-14
申请号：US15676752
申请日：2017-08-14
Applicant: Apple Inc.
Inventor： Greg M. Hess , Hemangi U. Gajjewar , Sachmanik Cheema
IPC: H03K5/159 , H03K19/0175
Abstract: An apparatus for delaying a signal transition is disclosed. The apparatus includes a first circuit coupled to a first power supply signal and a second, different power supply signal. The first circuit may be configured to, based on a voltage level of a logic signal, sink a current from an intermediate circuit node. A value of the current may be based upon a voltage level of the second different power supply signal. The apparatus also includes a second circuit coupled to the first power supply signal. The second circuit may be configured to generate an output signal based upon a voltage level of the intermediate circuit node. An amount of time between a transition of the logic signal and a corresponding transition of the output signal may be based on an amount of the current.
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Patent Agency Ranking
公开(公告)号：US09455000B2
公开(公告)日：2016-09-27
申请号：US14624605
申请日：2015-02-18
Applicant: Apple Inc.
Inventor： Ramesh Arvapalli , Greg M. Hess
Abstract: A first plurality of storage cells may be coupled to a first pair of data lines, and a second plurality of storage cells may be coupled to a second pair of data lines. Each storage cell in the first plurality of storage cells may be configured to generate a first output signal on the first pair of data lines in response to an assertion of a respective one of first plurality of selection signals, and each storage cell in the second plurality of storage cells may be configured to generate a second output signal on the second pair of data lines in response to the assertion of a respective one of a second plurality of selection signals. Circuitry may assert a given selection signal from either the first or second plurality of selection signals. An amplifier circuit may amplify either the first or second output signal.
Abstract translation: 第一多个存储单元可以耦合到第一对数据线，并且第二多个存储单元可以耦合到第二对数据线。 第一多个存储单元中的每个存储单元可以被配置为响应于第一多个选择信号中的相应一个选择信号的断言而在第一对数据线上产生第一输出信号，并且第二多个存储单元中的每个存储单元 存储单元可以被配置为响应于第二多个选择信号中的相应一个的断言而在第二对数据线上产生第二输出信号。 电路可以从第一或第二多个选择信号中断一个给定的选择信号。 放大器电路可以放大第一或第二输出信号。
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公开(公告)号：US20150089250A1
公开(公告)日：2015-03-26
申请号：US14036749
申请日：2013-09-25
Applicant: Apple Inc.
Inventor： Greg M. Hess
IPC: G06F1/26
CPC classification number: G06F1/263 , G11C5/148 , G11C7/20 , H03K19/018585
Abstract: A method and apparatus for preventing contention during the sequenced power up of an electronic system is disclosed. In one embodiment, an apparatus includes first and second power domains configured to receive power from first and second power sources, respectively. During a power up sequence, the first power source is configured to provide power prior to the second power source. A power detection circuit is configured to detect the presence of power from both of the first and second power sources. If power has not been detected from the second power source, a signal provided to a clamping circuit is asserted. When the signal is asserted by the power detection circuit, the clamping circuit may inhibit the control signal received from the second power domain from being provided to a power switch in the first power domain.
Abstract translation: 公开了一种用于在电子系统的顺序上电期间防止争用的方法和装置。 在一个实施例中，一种装置包括分别从第一和第二电源接收功率的第一和第二功率域。 在上电序列期间，第一电源被配置为在第二电源之前提供电力。 功率检测电路被配置为检测来自第一和第二电源的功率的存在。 如果没有从第二电源检测到电源，则断言提供给钳位电路的信号。 当由功率检测电路确定信号时，钳位电路可以禁止从第二电源域接收的控制信号提供给第一电源域中的电源开关。
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公开(公告)号：US20140126312A1
公开(公告)日：2014-05-08
申请号：US13670813
申请日：2012-11-07
Applicant: APPLE INC.
Inventor： Greg M. Hess , James E. Burnette, II
IPC: H03F3/45 , G01R31/316 , G11C29/00
CPC classification number: H01L22/12 , G11C29/026 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier.
Abstract translation: 公开了可以允许检测软故障的读出放大器测试电路的实施例。 读出放大器测试电路可以包括电压发生器电路，读出放大器和检测电路。 电压发生器可操作以可控制地向感测放大器提供不同的差分电压，并且检测电路可以用于检测读出放大器的输出上的模拟电压。
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公开(公告)号：US20220269617A1
公开(公告)日：2022-08-25
申请号：US17662500
申请日：2022-05-09
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Ben D. Jarrett , Edward M. McCombs , Greg M. Hess
Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
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公开(公告)号：US20220101914A1
公开(公告)日：2022-03-31
申请号：US17317844
申请日：2021-05-11
Applicant: Apple Inc.
Inventor： Michael A. Dreesen , Ajay Bhatia , Michael R. Seningen , Greg M. Hess , Siddhesh Gaiki
IPC: G11C11/412 , G11C11/419 , G06F7/523
Abstract: A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.
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